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mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling

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SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably
use high speed enable bit for other purpose. So this bit
shouldn't be changed for high speed enabling for this type of
SD controller.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
yangbo lu 2017-08-15 10:16:47 +08:00 committed by Ulf Hansson
parent 5b7f5eafb4
commit 501639bf21
1 changed files with 14 additions and 13 deletions
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27
drivers/mmc/host/sdhci.c
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@ -1640,19 +1640,20 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if ((ios->timing == MMC_TIMING_SD_HS || if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
ios->timing == MMC_TIMING_MMC_HS || if (ios->timing == MMC_TIMING_SD_HS ||
ios->timing == MMC_TIMING_MMC_HS400 || ios->timing == MMC_TIMING_MMC_HS ||
ios->timing == MMC_TIMING_MMC_HS200 || ios->timing == MMC_TIMING_MMC_HS400 ||
ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_MMC_HS200 ||
ios->timing == MMC_TIMING_UHS_SDR50 || ios->timing == MMC_TIMING_MMC_DDR52 ||
ios->timing == MMC_TIMING_UHS_SDR104 || ios->timing == MMC_TIMING_UHS_SDR50 ||
ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_UHS_SDR104 ||
ios->timing == MMC_TIMING_UHS_SDR25) ios->timing == MMC_TIMING_UHS_DDR50 ||
&& !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) ios->timing == MMC_TIMING_UHS_SDR25)
ctrl |= SDHCI_CTRL_HISPD; ctrl |= SDHCI_CTRL_HISPD;
else else
ctrl &= ~SDHCI_CTRL_HISPD; ctrl &= ~SDHCI_CTRL_HISPD;
}
if (host->version >= SDHCI_SPEC_300) { if (host->version >= SDHCI_SPEC_300) {
u16 clk, ctrl_2; u16 clk, ctrl_2;