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mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -1640,19 +1640,20 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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if ((ios->timing == MMC_TIMING_SD_HS ||
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ios->timing == MMC_TIMING_MMC_HS ||
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ios->timing == MMC_TIMING_MMC_HS400 ||
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ios->timing == MMC_TIMING_MMC_HS200 ||
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ios->timing == MMC_TIMING_MMC_DDR52 ||
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ios->timing == MMC_TIMING_UHS_SDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR104 ||
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ios->timing == MMC_TIMING_UHS_DDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR25)
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&& !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
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ctrl |= SDHCI_CTRL_HISPD;
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else
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ctrl &= ~SDHCI_CTRL_HISPD;
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if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
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if (ios->timing == MMC_TIMING_SD_HS ||
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ios->timing == MMC_TIMING_MMC_HS ||
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ios->timing == MMC_TIMING_MMC_HS400 ||
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ios->timing == MMC_TIMING_MMC_HS200 ||
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ios->timing == MMC_TIMING_MMC_DDR52 ||
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ios->timing == MMC_TIMING_UHS_SDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR104 ||
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ios->timing == MMC_TIMING_UHS_DDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR25)
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ctrl |= SDHCI_CTRL_HISPD;
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else
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ctrl &= ~SDHCI_CTRL_HISPD;
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}
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if (host->version >= SDHCI_SPEC_300) {
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u16 clk, ctrl_2;
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