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drm/i915/tgl: Move and restrict Wa_1408615072

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Following the changes in the previous patch
"drm/i915/gen11: Moving WAs to rcs_engine_wa_init()" also moving TGL
Wa_1408615072 to rcs_engine_wa_init() this way after a engine
reset it will be reapplied also restricting it to A0 as it is fixed in
B0 stepping.

BSpec: 52890
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302231421.224322-2-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2020-03-02 15:14:21 -08:00
parent 3551ff9287
commit 50148a25f8
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -1380,6 +1380,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_14010229206:tgl * Wa_14010229206:tgl
*/ */
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/* Wa_1408615072:tgl */
wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
} }
if (IS_TIGERLAKE(i915)) { if (IS_TIGERLAKE(i915)) {

4
drivers/gpu/drm/i915/intel_pm.c
View File

@ -6816,10 +6816,6 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
u32 vd_pg_enable = 0; u32 vd_pg_enable = 0;
unsigned int i; unsigned int i;
/* Wa_1408615072:tgl */
intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
0, VSUNIT_CLKGATE_DIS_TGL);
/* This is not a WA. Enable VD HCP & MFX_ENC powergate */ /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
for (i = 0; i < I915_MAX_VCS; i++) { for (i = 0; i < I915_MAX_VCS; i++) {
if (HAS_ENGINE(dev_priv, _VCS(i))) if (HAS_ENGINE(dev_priv, _VCS(i)))