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drm/i915/tgl: Move and restrict Wa_1408615072
Following the changes in the previous patch "drm/i915/gen11: Moving WAs to rcs_engine_wa_init()" also moving TGL Wa_1408615072 to rcs_engine_wa_init() this way after a engine reset it will be reapplied also restricting it to A0 as it is fixed in B0 stepping. BSpec: 52890 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200302231421.224322-2-jose.souza@intel.com
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@ -1380,6 +1380,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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* Wa_14010229206:tgl
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*/
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wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
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/* Wa_1408615072:tgl */
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wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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VSUNIT_CLKGATE_DIS_TGL);
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}
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if (IS_TIGERLAKE(i915)) {
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@ -6816,10 +6816,6 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
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u32 vd_pg_enable = 0;
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unsigned int i;
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/* Wa_1408615072:tgl */
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
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0, VSUNIT_CLKGATE_DIS_TGL);
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/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
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for (i = 0; i < I915_MAX_VCS; i++) {
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if (HAS_ENGINE(dev_priv, _VCS(i)))
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