ARM: Kirkwood: Fix DT based DSA.

During the conversion of boards to use DT to instantiate Distributed
Switch Architecture, nobody volunteered to test. As to be expected,
the conversion was flawed. Testers and access to hardware has now
become available, and this patch hopefully fixes the problems.

dsa,mii-bus must be a phandle to the top level mdio node, not the port
specific subnode of the mdio device.

dsa,ethernet must be a phandle to the port subnode within the ethernet
DT node, not the ethernet node.

Don't pinctrl hog the card detect gpio for mvsdio.

Rename the .dts files to make it clearer which file is for the Z0
stepping and which for the A0 or later stepping.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Cc: seugene@marvell.com
Tested-by: Eugene Sanivsky <seugene@marvell.com>
Fixes: e2eaa339af: ("ARM: Kirkwood: convert rd88f6281-setup.c to DT.")
Fixes: e7c8f3808b: ("ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT")
Cc: <stable@vger.kernel.org> #v3.15+
Link: https://lkml.kernel.org/r/1409592941-22244-1-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Andrew Lunn 2014-09-01 19:35:41 +02:00 committed by Jason Cooper
parent 500abb6ccb
commit 4f5e01e96d
7 changed files with 69 additions and 69 deletions

View File

@ -144,8 +144,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \
kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-a0.dtb \
kirkwood-rd88f6281-a1.dtb \
kirkwood-rd88f6281-z0.dtb \
kirkwood-rd88f6281-a.dtb \
kirkwood-rs212.dtb \
kirkwood-rs409.dtb \
kirkwood-rs411.dtb \

View File

@ -123,11 +123,11 @@ button@2 {
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&ethphy0>;
dsa,ethernet = <&eth0port>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
@ -169,17 +169,13 @@ port@5 {
&mdio {
status = "okay";
ethphy0: ethernet-phy@ff {
reg = <0xff>; /* No phy attached */
speed = <1000>;
duplex = <1>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
speed = <1000>;
duplex = <1>;
};
};

View File

@ -0,0 +1,43 @@
/*
* Marvell RD88F6181 A Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A0 or
* higher stepping of the SoC. The ethernet switch does not have a
* "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
reg = <10 0>; /* MDIO address 10, switch 0 in tree */
};
};
};
&mdio {
status = "okay";
ethphy1: ethernet-phy@11 {
reg = <11>;
};
};
&eth1 {
status = "okay";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
};
};

View File

@ -1,26 +0,0 @@
/*
* Marvell RD88F6181 A0 Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A0 variant of
* the SoC. The ethernet switch does not have a "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A0 SoC";
compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
reg = <10 0>; /* MDIO address 10, switch 0 in tree */
};
};
};

View File

@ -1,5 +1,5 @@
/*
* Marvell RD88F6181 A1 Board descrition
* Marvell RD88F6181 Z0 stepping descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
@ -7,17 +7,17 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A1 variant of
* the SoC. The ethernet switch has a "wan" port.
*/
* This file contains the definitions for the board using the Z0
* stepping of the SoC. The ethernet switch has a "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A1 SoC";
compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
model = "Marvell RD88f6281 Reference design, with Z0 SoC";
compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
@ -28,4 +28,8 @@ port@4 {
};
};
};
};
};
&eth1 {
status = "disabled";
};

View File

@ -37,7 +37,6 @@ pcie@1,0 {
ocp@f1000000 {
pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_sdio_cd>;
pinctrl-names = "default";
pmx_sdio_cd: pmx-sdio-cd {
@ -69,8 +68,8 @@ dsa@0 {
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&ethphy1>;
dsa,ethernet = <&eth0port>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
@ -119,35 +118,19 @@ partition@100000 {
};
partition@300000 {
label = "data";
label = "rootfs";
reg = <0x0300000 0x500000>;
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@ff {
reg = <0xff>; /* No PHY attached */
speed = <1000>;
duple = <1>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
};
};
&eth1 {
status = "okay";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
speed = <1000>;
duplex = <1>;
};
};

View File

@ -309,7 +309,7 @@ eth0: ethernet-controller@72000 {
marvell,tx-checksum-limit = <1600>;
status = "disabled";
ethernet0-port@0 {
eth0port: ethernet0-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <11>;
@ -342,7 +342,7 @@ eth1: ethernet-controller@76000 {
pinctrl-names = "default";
status = "disabled";
ethernet1-port@0 {
eth1port: ethernet1-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <15>;