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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: fix pipeconf dither bit definitions
Make them match the others and add BPP definitions. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -2078,11 +2078,6 @@
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/* Display & cursor control */
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/* dithering flag on Ironlake */
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#define PIPE_ENABLE_DITHER (1 << 4)
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#define PIPE_DITHER_TYPE_MASK (3 << 2)
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#define PIPE_DITHER_TYPE_SPATIAL (0 << 2)
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#define PIPE_DITHER_TYPE_ST01 (1 << 2)
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/* Pipe A */
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#define PIPEADSL 0x70000
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#define DSL_LINEMASK 0x00000fff
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@ -2101,6 +2096,17 @@
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
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#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
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#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
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#define PIPECONF_BPP_MASK (0x000000e0)
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#define PIPECONF_BPP_8 (0<<5)
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#define PIPECONF_BPP_10 (1<<5)
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#define PIPECONF_BPP_6 (2<<5)
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#define PIPECONF_BPP_12 (3<<5)
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#define PIPECONF_DITHER_EN (1<<4)
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#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
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#define PIPECONF_DITHER_TYPE_SP (0<<2)
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#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
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#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
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#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
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#define PIPEASTAT 0x70024
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#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
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#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
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@ -3910,8 +3910,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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if (HAS_PCH_SPLIT(dev)) {
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pipeconf &= ~PIPE_ENABLE_DITHER;
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pipeconf &= ~PIPE_DITHER_TYPE_MASK;
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pipeconf &= ~PIPECONF_DITHER_EN;
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pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
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}
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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@ -3955,8 +3955,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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if (IS_I965G(dev)) {
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if (dev_priv->lvds_dither) {
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if (HAS_PCH_SPLIT(dev)) {
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pipeconf |= PIPE_ENABLE_DITHER;
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pipeconf |= PIPE_DITHER_TYPE_ST01;
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pipeconf |= PIPECONF_DITHER_EN;
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pipeconf |= PIPECONF_DITHER_TYPE_ST1;
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} else
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lvds |= LVDS_ENABLE_DITHER;
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} else {
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