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drm/amd/powerplay: add display_config_changed for SMU11.
add display_config_changed to support sys interface for SMU11. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1376,6 +1376,48 @@ vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
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return ret;
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}
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static int vega20_display_config_changed(struct smu_context *smu)
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{
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int ret = 0;
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struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
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if (!smu->funcs)
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return -EINVAL;
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if (!smu->smu_dpm.dpm_context ||
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!smu->smu_table.tables ||
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!smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
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return -EINVAL;
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smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
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ret = vega20_set_uclk_to_highest_dpm_level(smu,
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&dpm_table->mem_table);
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if (ret) {
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pr_err("Failed to set uclk to highest dpm level");
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return ret;
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}
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if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
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!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
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ret = smu->funcs->write_watermarks_table(smu);
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if (ret) {
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pr_err("Failed to update WMTABLE!");
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return ret;
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}
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smu->watermarks_bitmap |= WATERMARKS_LOADED;
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}
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if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
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smu_feature_is_supported(smu, FEATURE_DPM_DCEFCLK_BIT) &&
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smu_feature_is_supported(smu, FEATURE_DPM_SOCCLK_BIT)) {
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smu_send_smc_msg_with_param(smu,
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SMU_MSG_NumOfDisplays,
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smu->display_config->num_display);
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}
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return ret;
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}
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static const struct pptable_funcs vega20_ppt_funcs = {
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.alloc_dpm_context = vega20_allocate_dpm_context,
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.store_powerplay_table = vega20_store_powerplay_table,
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