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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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phy: sr-usb: Add Stingray USB PHY driver
USB PHY driver supports two types of stingray USB PHYs - Type 1 is a combo PHY contains two PHYs, one SS and one HS. - Type 2 is a single HS PHY. These two PHY versons support both Generic xHCI host controller driver and BDC Broadcom device controller driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Srinath Mannam
Kishon Vijay Abraham I
parent
30417ab2a3
commit
4dcddbb38b
@ -10,6 +10,17 @@ config PHY_CYGNUS_PCIE
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Enable this to support the Broadcom Cygnus PCIe PHY.
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If unsure, say N.
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config PHY_BCM_SR_USB
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tristate "Broadcom Stingray USB PHY driver"
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depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST)
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select GENERIC_PHY
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default ARCH_BCM_IPROC
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help
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Enable this to support the Broadcom Stingray USB PHY
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driver. It supports all versions of Superspeed and
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Highspeed PHYs.
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If unsure, say N.
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config BCM_KONA_USB2_PHY
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tristate "Broadcom Kona USB2 PHY Driver"
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depends on HAS_IOMEM
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@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o
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phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o
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obj-$(CONFIG_PHY_BCM_SR_PCIE) += phy-bcm-sr-pcie.o
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obj-$(CONFIG_PHY_BCM_SR_USB) += phy-bcm-sr-usb.o
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394
drivers/phy/broadcom/phy-bcm-sr-usb.c
Normal file
394
drivers/phy/broadcom/phy-bcm-sr-usb.c
Normal file
@ -0,0 +1,394 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Broadcom
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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enum bcm_usb_phy_version {
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BCM_SR_USB_COMBO_PHY,
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BCM_SR_USB_HS_PHY,
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};
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enum bcm_usb_phy_reg {
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PLL_NDIV_FRAC,
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PLL_NDIV_INT,
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PLL_CTRL,
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PHY_CTRL,
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PHY_PLL_CTRL,
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};
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/* USB PHY registers */
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static const u8 bcm_usb_combo_phy_ss[] = {
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[PLL_CTRL] = 0x18,
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[PHY_CTRL] = 0x14,
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};
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static const u8 bcm_usb_combo_phy_hs[] = {
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[PLL_NDIV_FRAC] = 0x04,
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[PLL_NDIV_INT] = 0x08,
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[PLL_CTRL] = 0x0c,
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[PHY_CTRL] = 0x10,
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};
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#define HSPLL_NDIV_INT_VAL 0x13
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#define HSPLL_NDIV_FRAC_VAL 0x1005
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static const u8 bcm_usb_hs_phy[] = {
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[PLL_NDIV_FRAC] = 0x0,
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[PLL_NDIV_INT] = 0x4,
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[PLL_CTRL] = 0x8,
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[PHY_CTRL] = 0xc,
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};
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enum pll_ctrl_bits {
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PLL_RESETB,
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SSPLL_SUSPEND_EN,
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PLL_SEQ_START,
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PLL_LOCK,
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PLL_PDIV,
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};
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static const u8 u3pll_ctrl[] = {
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[PLL_RESETB] = 0,
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[SSPLL_SUSPEND_EN] = 1,
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[PLL_SEQ_START] = 2,
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[PLL_LOCK] = 3,
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};
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#define HSPLL_PDIV_MASK 0xF
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#define HSPLL_PDIV_VAL 0x1
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static const u8 u2pll_ctrl[] = {
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[PLL_PDIV] = 1,
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[PLL_RESETB] = 5,
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[PLL_LOCK] = 6,
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};
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enum bcm_usb_phy_ctrl_bits {
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CORERDY,
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AFE_LDO_PWRDWNB,
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AFE_PLL_PWRDWNB,
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AFE_BG_PWRDWNB,
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PHY_ISO,
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PHY_RESETB,
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PHY_PCTL,
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};
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#define PHY_PCTL_MASK 0xffff
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/*
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* 0x0806 of PCTL_VAL has below bits set
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* BIT-8 : refclk divider 1
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* BIT-3:2: device mode; mode is not effect
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* BIT-1: soft reset active low
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*/
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#define HSPHY_PCTL_VAL 0x0806
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#define SSPHY_PCTL_VAL 0x0006
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static const u8 u3phy_ctrl[] = {
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[PHY_RESETB] = 1,
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[PHY_PCTL] = 2,
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};
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static const u8 u2phy_ctrl[] = {
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[CORERDY] = 0,
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[AFE_LDO_PWRDWNB] = 1,
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[AFE_PLL_PWRDWNB] = 2,
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[AFE_BG_PWRDWNB] = 3,
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[PHY_ISO] = 4,
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[PHY_RESETB] = 5,
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[PHY_PCTL] = 6,
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};
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struct bcm_usb_phy_cfg {
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uint32_t type;
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uint32_t version;
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void __iomem *regs;
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struct phy *phy;
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const u8 *offset;
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};
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#define PLL_LOCK_RETRY_COUNT 1000
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enum bcm_usb_phy_type {
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USB_HS_PHY,
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USB_SS_PHY,
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};
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#define NUM_BCM_SR_USB_COMBO_PHYS 2
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static inline void bcm_usb_reg32_clrbits(void __iomem *addr, uint32_t clear)
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{
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writel(readl(addr) & ~clear, addr);
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}
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static inline void bcm_usb_reg32_setbits(void __iomem *addr, uint32_t set)
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{
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writel(readl(addr) | set, addr);
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}
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static int bcm_usb_pll_lock_check(void __iomem *addr, u32 bit)
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{
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int retry;
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u32 rd_data;
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retry = PLL_LOCK_RETRY_COUNT;
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do {
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rd_data = readl(addr);
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if (rd_data & bit)
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return 0;
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udelay(1);
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} while (--retry > 0);
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pr_err("%s: FAIL\n", __func__);
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return -ETIMEDOUT;
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}
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static int bcm_usb_ss_phy_init(struct bcm_usb_phy_cfg *phy_cfg)
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{
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int ret = 0;
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void __iomem *regs = phy_cfg->regs;
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const u8 *offset;
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u32 rd_data;
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offset = phy_cfg->offset;
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/* Set pctl with mode and soft reset */
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rd_data = readl(regs + offset[PHY_CTRL]);
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rd_data &= ~(PHY_PCTL_MASK << u3phy_ctrl[PHY_PCTL]);
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rd_data |= (SSPHY_PCTL_VAL << u3phy_ctrl[PHY_PCTL]);
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writel(rd_data, regs + offset[PHY_CTRL]);
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bcm_usb_reg32_clrbits(regs + offset[PLL_CTRL],
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BIT(u3pll_ctrl[SSPLL_SUSPEND_EN]));
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bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
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BIT(u3pll_ctrl[PLL_SEQ_START]));
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bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
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BIT(u3pll_ctrl[PLL_RESETB]));
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/* Maximum timeout for PLL reset done */
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msleep(30);
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ret = bcm_usb_pll_lock_check(regs + offset[PLL_CTRL],
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BIT(u3pll_ctrl[PLL_LOCK]));
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return ret;
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}
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static int bcm_usb_hs_phy_init(struct bcm_usb_phy_cfg *phy_cfg)
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{
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int ret = 0;
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void __iomem *regs = phy_cfg->regs;
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const u8 *offset;
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u32 rd_data;
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offset = phy_cfg->offset;
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writel(HSPLL_NDIV_INT_VAL, regs + offset[PLL_NDIV_INT]);
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writel(HSPLL_NDIV_FRAC_VAL, regs + offset[PLL_NDIV_FRAC]);
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rd_data = readl(regs + offset[PLL_CTRL]);
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rd_data &= ~(HSPLL_PDIV_MASK << u2pll_ctrl[PLL_PDIV]);
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rd_data |= (HSPLL_PDIV_VAL << u2pll_ctrl[PLL_PDIV]);
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writel(rd_data, regs + offset[PLL_CTRL]);
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/* Set Core Ready high */
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bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
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BIT(u2phy_ctrl[CORERDY]));
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/* Maximum timeout for Core Ready done */
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msleep(30);
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bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
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BIT(u2pll_ctrl[PLL_RESETB]));
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bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
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BIT(u2phy_ctrl[PHY_RESETB]));
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rd_data = readl(regs + offset[PHY_CTRL]);
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rd_data &= ~(PHY_PCTL_MASK << u2phy_ctrl[PHY_PCTL]);
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rd_data |= (HSPHY_PCTL_VAL << u2phy_ctrl[PHY_PCTL]);
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writel(rd_data, regs + offset[PHY_CTRL]);
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/* Maximum timeout for PLL reset done */
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msleep(30);
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ret = bcm_usb_pll_lock_check(regs + offset[PLL_CTRL],
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BIT(u2pll_ctrl[PLL_LOCK]));
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return ret;
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}
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static int bcm_usb_phy_reset(struct phy *phy)
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{
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struct bcm_usb_phy_cfg *phy_cfg = phy_get_drvdata(phy);
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void __iomem *regs = phy_cfg->regs;
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const u8 *offset;
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offset = phy_cfg->offset;
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if (phy_cfg->type == USB_HS_PHY) {
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bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL],
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BIT(u2phy_ctrl[CORERDY]));
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bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
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BIT(u2phy_ctrl[CORERDY]));
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}
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return 0;
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}
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static int bcm_usb_phy_init(struct phy *phy)
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{
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struct bcm_usb_phy_cfg *phy_cfg = phy_get_drvdata(phy);
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int ret = -EINVAL;
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if (phy_cfg->type == USB_SS_PHY)
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ret = bcm_usb_ss_phy_init(phy_cfg);
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else if (phy_cfg->type == USB_HS_PHY)
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ret = bcm_usb_hs_phy_init(phy_cfg);
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return ret;
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}
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static struct phy_ops sr_phy_ops = {
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.init = bcm_usb_phy_init,
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.reset = bcm_usb_phy_reset,
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.owner = THIS_MODULE,
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};
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static struct phy *bcm_usb_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct bcm_usb_phy_cfg *phy_cfg;
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int phy_idx;
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phy_cfg = dev_get_drvdata(dev);
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if (!phy_cfg)
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return ERR_PTR(-EINVAL);
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if (phy_cfg->version == BCM_SR_USB_COMBO_PHY) {
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phy_idx = args->args[0];
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if (WARN_ON(phy_idx > 1))
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return ERR_PTR(-ENODEV);
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return phy_cfg[phy_idx].phy;
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} else
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return phy_cfg->phy;
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}
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static int bcm_usb_phy_create(struct device *dev, struct device_node *node,
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void __iomem *regs, uint32_t version)
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{
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struct bcm_usb_phy_cfg *phy_cfg;
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int idx;
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if (version == BCM_SR_USB_COMBO_PHY) {
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phy_cfg = devm_kzalloc(dev, NUM_BCM_SR_USB_COMBO_PHYS *
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sizeof(struct bcm_usb_phy_cfg),
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GFP_KERNEL);
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if (!phy_cfg)
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return -ENOMEM;
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for (idx = 0; idx < NUM_BCM_SR_USB_COMBO_PHYS; idx++) {
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phy_cfg[idx].regs = regs;
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phy_cfg[idx].version = version;
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if (idx == 0) {
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phy_cfg[idx].offset = bcm_usb_combo_phy_hs;
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phy_cfg[idx].type = USB_HS_PHY;
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} else {
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phy_cfg[idx].offset = bcm_usb_combo_phy_ss;
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phy_cfg[idx].type = USB_SS_PHY;
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}
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phy_cfg[idx].phy = devm_phy_create(dev, node,
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&sr_phy_ops);
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if (IS_ERR(phy_cfg[idx].phy))
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return PTR_ERR(phy_cfg[idx].phy);
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phy_set_drvdata(phy_cfg[idx].phy, &phy_cfg[idx]);
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}
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} else if (version == BCM_SR_USB_HS_PHY) {
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phy_cfg = devm_kzalloc(dev, sizeof(struct bcm_usb_phy_cfg),
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GFP_KERNEL);
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if (!phy_cfg)
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return -ENOMEM;
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phy_cfg->regs = regs;
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phy_cfg->version = version;
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phy_cfg->offset = bcm_usb_hs_phy;
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phy_cfg->type = USB_HS_PHY;
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phy_cfg->phy = devm_phy_create(dev, node, &sr_phy_ops);
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if (IS_ERR(phy_cfg->phy))
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return PTR_ERR(phy_cfg->phy);
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phy_set_drvdata(phy_cfg->phy, phy_cfg);
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} else
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return -ENODEV;
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dev_set_drvdata(dev, phy_cfg);
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return 0;
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}
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static const struct of_device_id bcm_usb_phy_of_match[] = {
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{
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.compatible = "brcm,sr-usb-combo-phy",
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.data = (void *)BCM_SR_USB_COMBO_PHY,
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},
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{
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.compatible = "brcm,sr-usb-hs-phy",
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.data = (void *)BCM_SR_USB_HS_PHY,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, bcm_usb_phy_of_match);
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static int bcm_usb_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *dn = dev->of_node;
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const struct of_device_id *of_id;
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struct resource *res;
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void __iomem *regs;
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int ret;
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enum bcm_usb_phy_version version;
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struct phy_provider *phy_provider;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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of_id = of_match_node(bcm_usb_phy_of_match, dn);
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if (of_id)
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version = (enum bcm_usb_phy_version)of_id->data;
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else
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return -ENODEV;
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ret = bcm_usb_phy_create(dev, dn, regs, version);
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if (ret)
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return ret;
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phy_provider = devm_of_phy_provider_register(dev, bcm_usb_phy_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver bcm_usb_phy_driver = {
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.driver = {
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.name = "phy-bcm-sr-usb",
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.of_match_table = bcm_usb_phy_of_match,
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},
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.probe = bcm_usb_phy_probe,
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};
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module_platform_driver(bcm_usb_phy_driver);
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("Broadcom stingray USB Phy driver");
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MODULE_LICENSE("GPL v2");
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