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pci-v4.9-fixes-4
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYQKe0AAoJEFmIoMA60/r8dmsQAJ1BjfcgWunT8cyBjh9DW8MT mFj4w4qEtN8JthecXYKDHYY1zTRocuuKYQTCdX6qKnnx37amJwfiEtPsLqzoio3U HqIx0Nyereh6ir3VHJgITa2C0317pw6ti2rEZS+oMfQyWUDWVXMKOo3nsCKYtqLJ fO0K1ubYSUwNr1ph3rxTbJaycRUZsXK1PAdaROVeDjiw6IPgSNd9eboQCQAg3WQm JFsENhhCDM7qlFpwgbjtjv2IkzK0zpxs6vkVKRUJ1x8D2OAfg0j+rxYEVaOU23bO isj7rnbM1fFuC3WrAB1uexPfISLuzqUSIceB46EItoTJ7x3wmQGs4BIIt9LlmUte Z6RNAMbUx+K/5p2+xCVJAnbhfnCQv/vLkYEKpr2uPx43PywALYJq/8I4p/qh0zIW 562ulb7HUqh8jNMvFj/7kqCijnkFHw0iddL0zwC6VD5/lYiTeYN19/T00gUGLtB6 YWunN1G/fl/SdtI29oo8e+xVKuWraAsyKVX7LZIl2XaZhVBTy9vTC2wC/hdZqiMg yXK4/lE+Fr0tnHt8vVRgEicTHTmlQYQnRKNcy9PyDQWyYndg4ExacmsafQ61u0EE bUKoPPT7zJT/TVDp54cWk4t/AHc4TONNONNUH2xZKAMElsAiQrHd4GwFHUAQgz/C MiwbEXvfYTBcPCRP4cqD =DhJD -----END PGP SIGNATURE----- Merge tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "PCI fixes: - Fix Read Completion Boundary setting, which fixes a boot failure on IBM x3850 with Mellanox MT27500 ConnectX-3 - Update some MAINTAINERS entries and email addresses" * tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX) PCI: Export pcie_find_root_port PCI: designware-plat: Update author email PCI: designware: Change maintainer to Joao Pinto MAINTAINERS: Add devicetree binding to PCI i.MX6 entry MAINTAINERS: Update Richard Zhu's email address
This commit is contained in:
commit
4db5e636dd
13
MAINTAINERS
13
MAINTAINERS
@ -9257,11 +9257,12 @@ S: Maintained
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F: drivers/pci/host/*layerscape*
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PCI DRIVER FOR IMX6
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M: Richard Zhu <Richard.Zhu@freescale.com>
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M: Richard Zhu <hongxing.zhu@nxp.com>
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M: Lucas Stach <l.stach@pengutronix.de>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
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F: drivers/pci/host/*imx6*
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PCI DRIVER FOR TI KEYSTONE
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@ -9320,17 +9321,11 @@ F: drivers/pci/host/pci-exynos.c
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PCI DRIVER FOR SYNOPSIS DESIGNWARE
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M: Jingoo Han <jingoohan1@gmail.com>
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M: Pratyush Anand <pratyush.anand@gmail.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: drivers/pci/host/*designware*
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PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
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M: Jose Abreu <Jose.Abreu@synopsys.com>
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M: Joao Pinto <Joao.Pinto@synopsys.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/designware-pcie.txt
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F: drivers/pci/host/pcie-designware-plat.c
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F: drivers/pci/host/*designware*
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PCI DRIVER FOR GENERIC OF HOSTS
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M: Will Deacon <will.deacon@arm.com>
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpmpinto@gmail.com>
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* Authors: Joao Pinto <Joao.Pinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -307,20 +307,6 @@ static int pci_bus_set_aer_ops(struct pci_bus *bus)
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return 0;
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}
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static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
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{
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while (1) {
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if (!pci_is_pcie(dev))
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break;
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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return dev;
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if (!dev->bus->self)
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break;
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dev = dev->bus->self;
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}
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return NULL;
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}
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static int find_aer_device_iter(struct device *device, void *data)
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{
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struct pcie_device **result = data;
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@ -1439,6 +1439,21 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
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dev_warn(&dev->dev, "PCI-X settings not supported\n");
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}
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static bool pcie_root_rcb_set(struct pci_dev *dev)
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{
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struct pci_dev *rp = pcie_find_root_port(dev);
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u16 lnkctl;
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if (!rp)
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return false;
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pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
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if (lnkctl & PCI_EXP_LNKCTL_RCB)
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return true;
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return false;
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}
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static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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{
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int pos;
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@ -1468,9 +1483,20 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
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/* Initialize Link Control Register */
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if (pcie_cap_has_lnkctl(dev))
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if (pcie_cap_has_lnkctl(dev)) {
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/*
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* If the Root Port supports Read Completion Boundary of
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* 128, set RCB to 128. Otherwise, clear it.
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*/
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hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
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hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
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if (pcie_root_rcb_set(dev))
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hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
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pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
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~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
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}
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/* Find Advanced Error Reporting Enhanced Capability */
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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@ -1928,6 +1928,20 @@ static inline int pci_pcie_type(const struct pci_dev *dev)
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return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
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}
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static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
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{
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while (1) {
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if (!pci_is_pcie(dev))
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break;
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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return dev;
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if (!dev->bus->self)
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break;
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dev = dev->bus->self;
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}
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return NULL;
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}
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void pci_request_acs(void);
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bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
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bool pci_acs_path_enabled(struct pci_dev *start,
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