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[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC

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Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8541 CDS, MPC8544 DS, MPC8555 CDS, and MPC8568 MDS.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2007-05-15 13:20:05 -05:00 committed by Paul Mackerras
parent 50cf67075b
commit 4da421d620
4 changed files with 64 additions and 0 deletions
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16
arch/powerpc/boot/dts/mpc8541cds.dts
View File

@ -48,6 +48,22 @@ soc8541@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8541-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";

16
arch/powerpc/boot/dts/mpc8544ds.dts
View File

@ -48,6 +48,22 @@ soc8544@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,8544-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";

16
arch/powerpc/boot/dts/mpc8555cds.dts
View File

@ -48,6 +48,22 @@ soc8555@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";

16
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -57,6 +57,22 @@ soc8568@e0000000 {
reg = <e0000000 00100000>;
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8568-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";