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serial: 8250_dw: switch to use 8250_dwlib library
Since we have a common library module for Synopsys DesignWare UART, let us use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://lore.kernel.org/r/20190806094322.64987-4-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko
Greg Kroah-Hartman
parent
136e0ab99b
commit
4d5675c3b1
@ -27,66 +27,36 @@
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#include <asm/byteorder.h>
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#include "8250.h"
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#include "8250_dwlib.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_USR 0x1f /* UART Status Register */
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#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
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#define DW_UART_CPR 0xf4 /* Component Parameter Register */
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#define DW_UART_UCV 0xf8 /* UART Component Version */
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/* Component Parameter Register bits */
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#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
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#define DW_UART_CPR_AFCE_MODE (1 << 4)
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#define DW_UART_CPR_THRE_MODE (1 << 5)
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#define DW_UART_CPR_SIR_MODE (1 << 6)
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#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
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#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
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#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
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#define DW_UART_CPR_FIFO_STAT (1 << 10)
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#define DW_UART_CPR_SHADOW (1 << 11)
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#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
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#define DW_UART_CPR_DMA_EXTRA (1 << 13)
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#define DW_UART_CPR_FIFO_MODE (0xff << 16)
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/* Helper for fifo size calculation */
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#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
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/* DesignWare specific register fields */
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#define DW_UART_MCR_SIRE BIT(6)
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struct dw8250_data {
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struct dw8250_port_data data;
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u8 usr_reg;
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u8 dlf_size;
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int line;
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int msr_mask_on;
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int msr_mask_off;
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struct clk *clk;
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struct clk *pclk;
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struct reset_control *rst;
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struct uart_8250_dma dma;
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unsigned int skip_autocfg:1;
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unsigned int uart_16550_compatible:1;
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};
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static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
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static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
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{
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if (p->iotype == UPIO_MEM32BE)
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return ioread32be(p->membase + offset);
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return readl(p->membase + offset);
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}
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static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
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{
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if (p->iotype == UPIO_MEM32BE)
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iowrite32be(reg, p->membase + offset);
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else
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writel(reg, p->membase + offset);
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return container_of(data, struct dw8250_data, data);
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}
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static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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/* Override any modem control signals if needed */
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if (offset == UART_MSR) {
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@ -160,7 +130,7 @@ static void dw8250_tx_wait_empty(struct uart_port *p)
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static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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/* Allow the TX to drain before we reconfigure */
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if (offset == UART_LCR)
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@ -175,7 +145,7 @@ static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
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static void dw8250_serial_out(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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writeb(value, p->membase + (offset << p->regshift));
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@ -202,7 +172,7 @@ static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
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static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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value &= 0xff;
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__raw_writeq(value, p->membase + (offset << p->regshift));
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@ -216,7 +186,7 @@ static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
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static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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writel(value, p->membase + (offset << p->regshift));
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@ -233,7 +203,7 @@ static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
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static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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iowrite32be(value, p->membase + (offset << p->regshift));
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@ -252,7 +222,7 @@ static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
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static int dw8250_handle_irq(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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unsigned int iir = p->serial_in(p, UART_IIR);
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unsigned int status;
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unsigned long flags;
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@ -306,7 +276,7 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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struct dw8250_data *d = p->private_data;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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long rate;
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int ret;
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@ -368,37 +338,6 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
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return param == chan->device->dev;
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}
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/*
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* divisor = div(I) + div(F)
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* "I" means integer, "F" means fractional
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* quot = div(I) = clk / (16 * baud)
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* frac = div(F) * 2^dlf_size
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*
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* let rem = clk % (16 * baud)
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* we have: div(F) * (16 * baud) = rem
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* so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
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*/
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static unsigned int dw8250_get_divisor(struct uart_port *p,
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unsigned int baud,
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unsigned int *frac)
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{
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unsigned int quot, rem, base_baud = baud * 16;
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struct dw8250_data *d = p->private_data;
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quot = p->uartclk / base_baud;
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rem = p->uartclk % base_baud;
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*frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
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return quot;
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}
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static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
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unsigned int quot, unsigned int quot_frac)
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{
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dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
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serial8250_do_set_divisor(p, baud, quot, quot_frac);
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}
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static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
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{
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if (p->dev->of_node) {
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@ -437,59 +376,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
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/* Platforms with iDMA 64-bit */
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if (platform_get_resource_byname(to_platform_device(p->dev),
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IORESOURCE_MEM, "lpss_priv")) {
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data->dma.rx_param = p->dev->parent;
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data->dma.tx_param = p->dev->parent;
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data->dma.fn = dw8250_idma_filter;
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data->data.dma.rx_param = p->dev->parent;
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data->data.dma.tx_param = p->dev->parent;
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data->data.dma.fn = dw8250_idma_filter;
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}
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}
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static void dw8250_setup_port(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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u32 reg;
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/*
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* If the Component Version Register returns zero, we know that
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* ADDITIONAL_FEATURES are not enabled. No need to go any further.
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*/
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reg = dw8250_readl_ext(p, DW_UART_UCV);
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if (!reg)
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return;
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dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
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(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
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dw8250_writel_ext(p, DW_UART_DLF, ~0U);
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reg = dw8250_readl_ext(p, DW_UART_DLF);
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dw8250_writel_ext(p, DW_UART_DLF, 0);
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if (reg) {
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struct dw8250_data *d = p->private_data;
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d->dlf_size = fls(reg);
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p->get_divisor = dw8250_get_divisor;
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p->set_divisor = dw8250_set_divisor;
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}
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reg = dw8250_readl_ext(p, DW_UART_CPR);
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if (!reg)
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return;
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/* Select the type based on fifo */
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if (reg & DW_UART_CPR_FIFO_MODE) {
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p->type = PORT_16550A;
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p->flags |= UPF_FIXED_TYPE;
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p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
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up->capabilities = UART_CAP_FIFO;
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}
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if (reg & DW_UART_CPR_AFCE_MODE)
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up->capabilities |= UART_CAP_AFE;
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if (reg & DW_UART_CPR_SIR_MODE)
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up->capabilities |= UART_CAP_IRDA;
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}
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static int dw8250_probe(struct platform_device *pdev)
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{
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struct uart_8250_port uart = {}, *up = &uart;
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@ -534,9 +426,9 @@ static int dw8250_probe(struct platform_device *pdev)
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if (!data)
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return -ENOMEM;
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data->dma.fn = dw8250_fallback_dma_filter;
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data->data.dma.fn = dw8250_fallback_dma_filter;
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data->usr_reg = DW_UART_USR;
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p->private_data = data;
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p->private_data = &data->data;
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data->uart_16550_compatible = device_property_read_bool(dev,
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"snps,uart-16550-compatible");
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@ -632,14 +524,14 @@ static int dw8250_probe(struct platform_device *pdev)
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/* If we have a valid fifosize, try hooking up DMA */
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if (p->fifosize) {
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data->dma.rxconf.src_maxburst = p->fifosize / 4;
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data->dma.txconf.dst_maxburst = p->fifosize / 4;
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up->dma = &data->dma;
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data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
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data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
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up->dma = &data->data.dma;
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}
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data->line = serial8250_register_8250_port(up);
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if (data->line < 0) {
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err = data->line;
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data->data.line = serial8250_register_8250_port(up);
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if (data->data.line < 0) {
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err = data->data.line;
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goto err_reset;
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}
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@ -671,7 +563,7 @@ static int dw8250_remove(struct platform_device *pdev)
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pm_runtime_get_sync(dev);
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serial8250_unregister_port(data->line);
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serial8250_unregister_port(data->data.line);
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reset_control_assert(data->rst);
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@ -692,7 +584,7 @@ static int dw8250_suspend(struct device *dev)
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{
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struct dw8250_data *data = dev_get_drvdata(dev);
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serial8250_suspend_port(data->line);
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serial8250_suspend_port(data->data.line);
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return 0;
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}
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@ -701,7 +593,7 @@ static int dw8250_resume(struct device *dev)
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{
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struct dw8250_data *data = dev_get_drvdata(dev);
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serial8250_resume_port(data->line);
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serial8250_resume_port(data->data.line);
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return 0;
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}
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@ -357,6 +357,7 @@ config SERIAL_8250_FSL
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config SERIAL_8250_DW
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tristate "Support for Synopsys DesignWare 8250 quirks"
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depends on SERIAL_8250
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select SERIAL_8250_DWLIB
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help
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Selecting this option will enable handling of the extra features
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present in the Synopsys DesignWare APB UART.
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