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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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soc: samsung: pmu: Remove unused and duplicated defines
The exynos-regs-pmu.h was never a complete list of PMU registers. It contained a lot of holes for registers which were not used. However, a lot of unused defines came along with porting the code from vendor kernel. Few of defines were also duplicated. Remove them so the file will be slightly smaller. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Krzysztof Kozlowski
parent
6bce1974f6
commit
4cb3e37827
@ -7,7 +7,13 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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*
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*
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* Notice:
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* This is not a list of all Exynos Power Management Unit SFRs.
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* There are too many of them, not mentioning subtle differences
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* between SoCs. For now, put here only the used registers.
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*/
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#ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H
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#define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__
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@ -38,7 +44,6 @@
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#define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n)
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#define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28)
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#define EXYNOS_SWRESET 0x0400
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#define EXYNOS5440_SWRESET 0x00C4
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#define S5P_WAKEUP_STAT 0x0600
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#define S5P_EINT_WAKEUP_MASK 0x0604
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@ -136,12 +141,6 @@
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#define EXYNOS_COMMON_OPTION(_nr) \
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(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
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#define EXYNOS_CORE_LOCAL_PWR_EN 0x3
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#define EXYNOS_ARM_COMMON_STATUS 0x2504
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#define EXYNOS_COMMON_OPTION(_nr) \
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(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
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#define EXYNOS_ARM_L2_CONFIGURATION 0x2600
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#define EXYNOS_L2_CONFIGURATION(_nr) \
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(EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
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@ -149,18 +148,10 @@
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(EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
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#define EXYNOS_L2_OPTION(_nr) \
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(EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
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#define EXYNOS_L2_COMMON_PWR_EN 0x3
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#define EXYNOS_ARM_CORE_X_STATUS_OFFSET 0x4
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#define EXYNOS5_APLL_SYSCLK_CONFIGURATION 0x2A00
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#define EXYNOS5_APLL_SYSCLK_STATUS 0x2A04
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#define EXYNOS5_ARM_L2_OPTION 0x2608
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#define EXYNOS5_USE_RETENTION BIT(4)
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#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
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#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
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#define S5P_PAD_RET_MMC2_OPTION 0x30c8
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#define S5P_PAD_RET_GPIO_OPTION 0x3108
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@ -411,7 +402,6 @@
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#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
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#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
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#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
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#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
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#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
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#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
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#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
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@ -485,7 +475,6 @@
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#define EXYNOS5420_SWRESET_KFC_SEL 0x3
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/* Only for EXYNOS5420 */
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#define EXYNOS5420_ISP_ARM_OPTION 0x2488
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#define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3)
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#define EXYNOS5420_LPI_MASK 0x0004
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@ -494,9 +483,6 @@
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#define EXYNOS5420_ATB_KFC BIT(13)
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#define EXYNOS5420_ATB_ISP_ARM BIT(19)
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#define EXYNOS5420_EMULATION BIT(31)
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#define ATB_ISP_ARM BIT(12)
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#define ATB_KFC BIT(13)
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#define ATB_NOC BIT(14)
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#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100
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#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104
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@ -510,11 +496,6 @@
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#define EXYNOS5420_KFC_CORE_RESET(_nr) \
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((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr))
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#define EXYNOS5420_BB_CON1 0x0784
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#define EXYNOS5420_BB_SEL_EN BIT(31)
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#define EXYNOS5420_BB_PMOS_EN BIT(7)
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#define EXYNOS5420_BB_1300X 0XF
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#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020
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#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024
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#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028
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@ -546,15 +527,6 @@
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#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178
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#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8
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#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC
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#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR 0x11C0
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#define EXYNOS5420_USBDEV_MEM_SYS_PWR 0x11CC
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#define EXYNOS5420_USBDEV1_MEM_SYS_PWR 0x11D0
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#define EXYNOS5420_SDMMC_MEM_SYS_PWR 0x11D4
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#define EXYNOS5420_CSSYS_MEM_SYS_PWR 0x11D8
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#define EXYNOS5420_SECSS_MEM_SYS_PWR 0x11DC
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#define EXYNOS5420_ROTATOR_MEM_SYS_PWR 0x11E0
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#define EXYNOS5420_INTRAM_MEM_SYS_PWR 0x11E4
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#define EXYNOS5420_INTROM_MEM_SYS_PWR 0x11E8
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#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208
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#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210
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#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214
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@ -605,13 +577,7 @@
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#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C
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#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0
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#define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4
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#define EXYNOS_ARM_CORE2_CONFIGURATION 0x2100
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#define EXYNOS5420_ARM_CORE2_OPTION 0x2108
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#define EXYNOS_ARM_CORE3_CONFIGURATION 0x2180
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#define EXYNOS5420_ARM_CORE3_OPTION 0x2188
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#define EXYNOS5420_ARM_COMMON_STATUS 0x2504
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#define EXYNOS5420_ARM_COMMON_OPTION 0x2508
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#define EXYNOS5420_KFC_COMMON_STATUS 0x2584
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#define EXYNOS5420_KFC_COMMON_OPTION 0x2588
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#define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C
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@ -626,33 +592,9 @@
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#define EXYNOS_PAD_RET_DRAM_OPTION 0x3008
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#define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028
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#define EXYNOS_PAD_RET_JTAG_OPTION 0x3048
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#define EXYNOS_PAD_RET_GPIO_OPTION 0x3108
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#define EXYNOS_PAD_RET_UART_OPTION 0x3128
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#define EXYNOS_PAD_RET_MMCA_OPTION 0x3148
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#define EXYNOS_PAD_RET_MMCB_OPTION 0x3168
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#define EXYNOS_PAD_RET_EBIA_OPTION 0x3188
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#define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8
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#define EXYNOS_PS_HOLD_CONTROL 0x330C
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/* For SYS_PWR_REG */
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#define EXYNOS_SYS_PWR_CFG BIT(0)
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#define EXYNOS5420_MFC_CONFIGURATION 0x4060
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#define EXYNOS5420_MFC_STATUS 0x4064
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#define EXYNOS5420_MFC_OPTION 0x4068
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#define EXYNOS5420_G3D_CONFIGURATION 0x4080
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#define EXYNOS5420_G3D_STATUS 0x4084
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#define EXYNOS5420_G3D_OPTION 0x4088
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#define EXYNOS5420_DISP0_CONFIGURATION 0x40A0
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#define EXYNOS5420_DISP0_STATUS 0x40A4
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#define EXYNOS5420_DISP0_OPTION 0x40A8
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#define EXYNOS5420_DISP1_CONFIGURATION 0x40C0
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#define EXYNOS5420_DISP1_STATUS 0x40C4
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#define EXYNOS5420_DISP1_OPTION 0x40C8
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#define EXYNOS5420_MAU_CONFIGURATION 0x40E0
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#define EXYNOS5420_MAU_STATUS 0x40E4
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#define EXYNOS5420_MAU_OPTION 0x40E8
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#define EXYNOS5420_FSYS2_OPTION 0x4168
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#define EXYNOS5420_PSGEN_OPTION 0x4188
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