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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iwlwifi: HW bug fixes
This patch adds few HW bug fixes. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -93,6 +93,13 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
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iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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/* Set FH wait treshold to maximum (HW error during stress W/A) */
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iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
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/* enable HAP INTA to move device L1a -> L0s */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
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/* set "initialization complete" bit to move adapter
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@ -230,6 +237,14 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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/* W/A : NIC is stuck in a reset state after Early PCIe power off
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* (PCIe power is lost before PERST# is asserted),
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* causing ME FW to lose ownership and not being able to obtain it back.
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*/
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
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~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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@ -104,6 +104,7 @@
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* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
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*/
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
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#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
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/* Bits for CSR_HW_IF_CONFIG_REG */
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#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
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@ -118,7 +119,12 @@
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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#define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM (0x00400000)
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#define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN (0x02000000)
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#define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME (0x08000000)
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/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
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* acknowledged (reset) by host writing "1" to flagged bits. */
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@ -236,6 +242,8 @@
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#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
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#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
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/* HPET MEM debug */
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#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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/*
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@ -84,14 +84,16 @@
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#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
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#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
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#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
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#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
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#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
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#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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/**
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* BSM (Bootstrap State Machine)
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@ -3920,7 +3920,7 @@ void ieee80211_scan_completed(struct ieee80211_hw *hw)
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if (sdata->vif.type == IEEE80211_IF_TYPE_IBSS) {
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struct ieee80211_if_sta *ifsta = &sdata->u.sta;
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if (!(ifsta->flags & IEEE80211_STA_BSSID_SET) ||
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(!ifsta->state == IEEE80211_IBSS_JOINED &&
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(!(ifsta->state == IEEE80211_IBSS_JOINED) &&
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!ieee80211_sta_active_ibss(dev)))
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ieee80211_sta_find_ibss(dev, ifsta);
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}
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