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drm/i915/kbl: IPC workaround for kabylake

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Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.

KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.

Changes since V1:
 - Add Workaround number in commit & code
Changes since V2 (from Paulo):
 - Bikeshed the WA tag so it looks like the others

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-4-mahesh1.kumar@intel.com
This commit is contained in:
Mahesh Kumar 2016-12-01 21:19:35 +05:30 committed by Paulo Zanoni
parent a3a8986cb2
commit 4b7b233188
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/intel_pm.c
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@ -3596,6 +3596,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
fb->modifier == I915_FORMAT_MOD_Yf_TILED;
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
/* Display WA #1141: kbl. */
if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
latency += 4;
if (apply_memory_bw_wa && x_tiled)
latency += 15;