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clocksource/drivers/sun5i: Refactor the current code

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Refactor the code in order to remove the global variables and
split the clock source and clock events registration in order to
ease the addition of the clock notifiers needed to handle the
parent clock rate changes.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1427796746-373-4-git-send-email-daniel.lezcano@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Maxime Ripard 2015-03-31 12:12:25 +02:00 committed by Ingo Molnar
parent a45860d0ba
commit 4a59058f0b
1 changed files with 166 additions and 65 deletions
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231
drivers/clocksource/timer-sun5i.c
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@ -17,6 +17,7 @@
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -36,8 +37,27 @@
#define TIMER_SYNC_TICKS 3
static void __iomem *timer_base;
static u32 ticks_per_jiffy;
struct sun5i_timer {
void __iomem *base;
struct clk *clk;
u32 ticks_per_jiffy;
};
struct sun5i_timer_clksrc {
struct sun5i_timer timer;
struct clocksource clksrc;
};
#define to_sun5i_timer_clksrc(x) \
container_of(x, struct sun5i_timer_clksrc, clksrc)
struct sun5i_timer_clkevt {
struct sun5i_timer timer;
struct clock_event_device clkevt;
};
#define to_sun5i_timer_clkevt(x) \
container_of(x, struct sun5i_timer_clkevt, clkevt)
/*
* When we disable a timer, we need to wait at least for 2 cycles of
@ -45,30 +65,30 @@ static u32 ticks_per_jiffy;
* that is already setup and runs at the same frequency than the other
* timers, and we never will be disabled.
*/
static void sun5i_clkevt_sync(void)
static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
{
u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
cpu_relax();
}
static void sun5i_clkevt_time_stop(u8 timer)
static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
{
u32 val = readl(timer_base + TIMER_CTL_REG(timer));
writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
sun5i_clkevt_sync();
sun5i_clkevt_sync(ce);
}
static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
{
writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
}
static void sun5i_clkevt_time_start(u8 timer, bool periodic)
static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
{
u32 val = readl(timer_base + TIMER_CTL_REG(timer));
u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
if (periodic)
val &= ~TIMER_CTL_ONESHOT;
@ -76,66 +96,170 @@ static void sun5i_clkevt_time_start(u8 timer, bool periodic)
val |= TIMER_CTL_ONESHOT;
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
timer_base + TIMER_CTL_REG(timer));
ce->timer.base + TIMER_CTL_REG(timer));
}
static void sun5i_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
struct clock_event_device *clkevt)
{
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
sun5i_clkevt_time_stop(0);
sun5i_clkevt_time_setup(0, ticks_per_jiffy);
sun5i_clkevt_time_start(0, true);
sun5i_clkevt_time_stop(ce, 0);
sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
sun5i_clkevt_time_start(ce, 0, true);
break;
case CLOCK_EVT_MODE_ONESHOT:
sun5i_clkevt_time_stop(0);
sun5i_clkevt_time_start(0, false);
sun5i_clkevt_time_stop(ce, 0);
sun5i_clkevt_time_start(ce, 0, false);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
sun5i_clkevt_time_stop(0);
sun5i_clkevt_time_stop(ce, 0);
break;
}
}
static int sun5i_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
struct clock_event_device *clkevt)
{
sun5i_clkevt_time_stop(0);
sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
sun5i_clkevt_time_start(0, false);
struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
sun5i_clkevt_time_stop(ce, 0);
sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
sun5i_clkevt_time_start(ce, 0, false);
return 0;
}
static struct clock_event_device sun5i_clockevent = {
.name = "sun5i_tick",
.rating = 340,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = sun5i_clkevt_mode,
.set_next_event = sun5i_clkevt_next_event,
};
static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
writel(0x1, timer_base + TIMER_IRQ_ST_REG);
evt->event_handler(evt);
writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
ce->clkevt.event_handler(&ce->clkevt);
return IRQ_HANDLED;
}
static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
{
struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
}
static int __init sun5i_setup_clocksource(struct device_node *node,
void __iomem *base,
struct clk *clk, int irq)
{
struct sun5i_timer_clksrc *cs;
unsigned long rate;
int ret;
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
if (!cs)
return -ENOMEM;
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("Couldn't enable parent clock\n");
goto err_free;
}
rate = clk_get_rate(clk);
cs->timer.base = base;
cs->timer.clk = clk;
writel(~0, base + TIMER_INTVAL_LO_REG(1));
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
base + TIMER_CTL_REG(1));
cs->clksrc.name = node->name;
cs->clksrc.rating = 340;
cs->clksrc.read = sun5i_clksrc_read;
cs->clksrc.mask = CLOCKSOURCE_MASK(32);
cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
ret = clocksource_register_hz(&cs->clksrc, rate);
if (ret) {
pr_err("Couldn't register clock source.\n");
goto err_disable_clk;
}
return 0;
err_disable_clk:
clk_disable_unprepare(clk);
err_free:
kfree(cs);
return ret;
}
static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
struct clk *clk, int irq)
{
struct sun5i_timer_clkevt *ce;
unsigned long rate;
int ret;
u32 val;
ce = kzalloc(sizeof(*ce), GFP_KERNEL);
if (!ce)
return -ENOMEM;
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("Couldn't enable parent clock\n");
goto err_free;
}
rate = clk_get_rate(clk);
ce->timer.base = base;
ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
ce->timer.clk = clk;
ce->clkevt.name = node->name;
ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
ce->clkevt.set_next_event = sun5i_clkevt_next_event;
ce->clkevt.set_mode = sun5i_clkevt_mode;
ce->clkevt.rating = 340;
ce->clkevt.irq = irq;
ce->clkevt.cpumask = cpu_possible_mask;
/* Enable timer0 interrupt */
val = readl(base + TIMER_IRQ_EN_REG);
writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
clockevents_config_and_register(&ce->clkevt, rate,
TIMER_SYNC_TICKS, 0xffffffff);
ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
"sun5i_timer0", ce);
if (ret) {
pr_err("Unable to register interrupt\n");
goto err_disable_clk;
}
return 0;
err_disable_clk:
clk_disable_unprepare(clk);
err_free:
kfree(ce);
return ret;
}
static void __init sun5i_timer_init(struct device_node *node)
{
struct reset_control *rstc;
unsigned long rate;
void __iomem *timer_base;
struct clk *clk;
int ret, irq;
u32 val;
int irq;
timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
if (!timer_base)
@ -148,36 +272,13 @@ static void __init sun5i_timer_init(struct device_node *node)
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
rstc = of_reset_control_get(node, NULL);
if (!IS_ERR(rstc))
reset_control_deassert(rstc);
writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
timer_base + TIMER_CTL_REG(1));
clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
rate, 340, 32, clocksource_mmio_readl_down);
ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
/* Enable timer0 interrupt */
val = readl(timer_base + TIMER_IRQ_EN_REG);
writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
sun5i_clockevent.cpumask = cpu_possible_mask;
sun5i_clockevent.irq = irq;
clockevents_config_and_register(&sun5i_clockevent, rate,
TIMER_SYNC_TICKS, 0xffffffff);
ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
"sun5i_timer0", &sun5i_clockevent);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
sun5i_setup_clocksource(node, timer_base, clk, irq);
sun5i_setup_clockevent(node, timer_base, clk, irq);
}
CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
sun5i_timer_init);