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ARM: dts: r7s9210: Add RIIC support

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Add I2C support for the R7S9210 (RZ/A2) SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Chris Brandt 2019-04-30 08:23:06 -05:00 committed by Simon Horman
parent cbcb639172
commit 49da03c67c
1 changed files with 76 additions and 0 deletions
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76
arch/arm/boot/dts/r7s9210.dtsi
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@ -216,6 +216,82 @@ ether1: ethernet@e8204200 {
status = "disabled";
};
i2c0: i2c@e803a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
reg = <0xe803a000 0x44>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 87>;
power-domains = <&cpg>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@e803a400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
reg = <0xe803a400 0x44>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 86>;
power-domains = <&cpg>;
clock-frequency = <100000>;
status = "disabled";
};
i2c2: i2c@e803a800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
reg = <0xe803a800 0x44>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 85>;
power-domains = <&cpg>;
clock-frequency = <100000>;
status = "disabled";
};
i2c3: i2c@e803ac00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
reg = <0xe803ac00 0x44>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 84>;
power-domains = <&cpg>;
clock-frequency = <100000>;
status = "disabled";
};
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;