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ARM: dts: imx6q-sabresd: add pinctrl settings

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Add pinctrl settings for existing devices in imx6q-sabresd.dts.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo 2012-08-11 22:06:26 +08:00
parent 9e3c00665d
commit 497ae1747b
2 changed files with 50 additions and 1 deletions
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25
arch/arm/boot/dts/imx6q-sabresd.dts
View File

@ -22,28 +22,51 @@ memory {
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";

26
arch/arm/boot/dts/imx6q.dtsi
View File

@ -609,6 +609,15 @@ pinctrl_i2c1_1: i2c1grp-1 {
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
@ -627,6 +636,23 @@ pinctrl_uart4_1: uart4grp-1 {
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <