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drm/amd/display: implement bounding box update based on uclk breakdown
[why] Actual breakdown of DPM level varies by SKU (for the same family) DC needs some ability to ammend pre-silicon numbers Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -25,6 +25,8 @@
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#ifndef __DISPLAY_MODE_STRUCTS_H__
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#define __DISPLAY_MODE_STRUCTS_H__
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#define MAX_CLOCK_LIMIT_STATES 8
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typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
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typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
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typedef struct _vcs_dpi_ip_params_st ip_params_st;
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@ -103,7 +105,7 @@ struct _vcs_dpi_soc_bounding_box_st {
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double xfc_xbuf_latency_tolerance_us;
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int use_urgent_burst_bw;
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unsigned int num_states;
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struct _vcs_dpi_voltage_scaling_st clock_limits[8];
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struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
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};
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struct _vcs_dpi_ip_params_st {
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