mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-16 20:26:19 +07:00
arm64: dts: visconti: Add device tree for TMPV7708 RM main board
Add basic support for the Visconti TMPV7708 SoC peripherals -
- CPU
- CA53 x 4 and 2 cluster.
- not support PSCI, currently only spin-table is supported.
- Interrupt controller (ARM Generic Interrupt Controller)
- Timer (ARM architected timer)
- UART (ARM PL011 UART controller)
- SPI (ARM PL022 SPI controller)
- I2C (Synopsys DesignWare APB I2C Controller)
- Pin control (Visconti specific)
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp>
This commit is contained in:
Nobuhiro Iwamatsu
parent
0aa56c7eba
commit
48dea9a700
@ -27,5 +27,6 @@ subdir-y += socionext
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subdir-y += sprd
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subdir-y += synaptics
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subdir-y += ti
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subdir-y += toshiba
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subdir-y += xilinx
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subdir-y += zte
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2
arch/arm64/boot/dts/toshiba/Makefile
Normal file
2
arch/arm64/boot/dts/toshiba/Makefile
Normal file
@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb
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43
arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
Normal file
43
arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree File for TMPV7708 RM main board
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*
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* (C) Copyright 2020, Toshiba Corporation.
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* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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/dts-v1/;
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#include "tmpv7708.dtsi"
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/ {
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model = "Toshiba TMPV7708 RM main board";
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compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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/* 768MB memory */
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x30000000>;
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};
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};
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&uart0 {
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status = "okay";
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clocks = <&uart_clk>;
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clock-names = "apb_pclk";
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};
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&uart1 {
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status = "okay";
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clocks = <&uart_clk>;
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clock-names = "apb_pclk";
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};
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390
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
Normal file
390
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
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@ -0,0 +1,390 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Source for the TMPV7708
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*
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* (C) Copyright 2018 - 2020, Toshiba Corporation.
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* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
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/ {
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compatible = "toshiba,tmpv7708";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x00>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x01>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x02>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x03>;
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x102>;
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x81100000>;
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reg = <0x103>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts =
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<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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gic: interrupt-controller@24001000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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reg = <0 0x24001000 0 0x1000>,
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<0 0x24002000 0 0x2000>,
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<0 0x24004000 0 0x2000>,
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<0 0x24006000 0 0x2000>;
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};
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pmux: pmux@24190000 {
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compatible = "toshiba,tmpv7708-pinctrl";
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reg = <0 0x24190000 0 0x10000>;
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};
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uart0: serial@28200000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x28200000 0 0x1000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "disabled";
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};
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uart1: serial@28201000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x28201000 0 0x1000>;
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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uart2: serial@28202000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x28202000 0 0x1000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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uart3: serial@28203000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0x28203000 0 0x1000>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "disabled";
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};
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i2c0: i2c@28030000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28030000 0 0x1000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@28031000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28031000 0 0x1000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@28032000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28032000 0 0x1000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@28033000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28033000 0 0x1000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@28034000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28034000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@28035000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28035000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@28036000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28036000 0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c7: i2c@28037000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28037000 0 0x1000>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c8: i2c@28038000 {
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compatible = "snps,designware-i2c";
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reg = <0 0x28038000 0 0x1000>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c8_pins>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@28140000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28140000 0 0x1000>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@28141000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28141000 0 0x1000>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@28142000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28142000 0 0x1000>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@28143000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28143000 0 0x1000>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi3_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@28144000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28144000 0 0x1000>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi4_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@28145000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28145000 0 0x1000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi5_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi6: spi@28146000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0x28146000 0 0x1000>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi6_pins>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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#include "tmpv7708_pins.dtsi"
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93
arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
Normal file
93
arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
Normal file
@ -0,0 +1,93 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
&pmux {
|
||||
spi0_pins: spi0-pins {
|
||||
function = "spi0";
|
||||
groups = "spi0_grp";
|
||||
};
|
||||
spi1_pins: spi1-pins {
|
||||
function = "spi1";
|
||||
groups = "spi1_grp";
|
||||
};
|
||||
spi2_pins: spi2-pins {
|
||||
function = "spi2";
|
||||
groups = "spi2_grp";
|
||||
};
|
||||
spi3_pins: spi3-pins {
|
||||
function = "spi3";
|
||||
groups = "spi3_grp";
|
||||
};
|
||||
spi4_pins: spi4-pins {
|
||||
function = "spi4";
|
||||
groups = "spi4_grp";
|
||||
};
|
||||
spi5_pins: spi5-pins {
|
||||
function = "spi5";
|
||||
groups = "spi5_grp";
|
||||
};
|
||||
spi6_pins: spi6-pins {
|
||||
function = "spi6";
|
||||
groups = "spi6_grp";
|
||||
};
|
||||
uart0_pins: uart0-pins {
|
||||
function = "uart0";
|
||||
groups = "uart0_grp";
|
||||
};
|
||||
uart1_pins: uart1-pins {
|
||||
function = "uart1";
|
||||
groups = "uart1_grp";
|
||||
};
|
||||
uart2_pins: uart2-pins {
|
||||
function = "uart2";
|
||||
groups = "uart2_grp";
|
||||
};
|
||||
uart3_pins: uart3-pins {
|
||||
function = "uart3";
|
||||
groups = "uart3_grp";
|
||||
};
|
||||
i2c0_pins: i2c0-pins {
|
||||
function = "i2c0";
|
||||
groups = "i2c0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c1_pins: i2c1-pins {
|
||||
function = "i2c1";
|
||||
groups = "i2c1_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c2_pins: i2c2-pins {
|
||||
function = "i2c2";
|
||||
groups = "i2c2_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c3_pins: i2c3-pins {
|
||||
function = "i2c3";
|
||||
groups = "i2c3_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c4_pins: i2c4-pins {
|
||||
function = "i2c4";
|
||||
groups = "i2c4_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c5_pins: i2c5-pins {
|
||||
function = "i2c5";
|
||||
groups = "i2c5_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c6_pins: i2c6-pins {
|
||||
function = "i2c6";
|
||||
groups = "i2c6_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c7_pins: i2c7-pins {
|
||||
function = "i2c7";
|
||||
groups = "i2c7_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c8_pins: i2c8-pins {
|
||||
function = "i2c8";
|
||||
groups = "i2c8_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user