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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: LPC32xx: USB Support
This patch adds OHCI support to the LPC32xx ARM platform. Besides the trivial addition of platform "usb-ohci" support, fixes for the USB PLL have been added to arch/arm/mach-lpc32xx/clock.c, ported from NXP's lpclinux.com. (This is the mach-lpc32xx specific part, the USB subsystem specific changes are in a separate patch for the USB maintainers.) Signed-off-by: Roland Stigge <stigge@antcom.de>
This commit is contained in:
Roland Stigge
parent
a7e4c6a714
commit
48a5dedfa7
@ -87,6 +87,7 @@
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/amba/bus.h>
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@ -100,6 +101,8 @@
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static DEFINE_SPINLOCK(global_clkregs_lock);
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static int usb_pll_enable, usb_pll_valid;
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static struct clk clk_armpll;
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static struct clk clk_usbpll;
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@ -384,30 +387,62 @@ static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
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static int local_usbpll_enable(struct clk *clk, int enable)
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{
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u32 reg;
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int ret = -ENODEV;
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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int ret = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(20);
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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if (enable == 0) {
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reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
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LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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} else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
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__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
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LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
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LPC32XX_CLKPWR_USB_CTRL);
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__raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
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LPC32XX_CLKPWR_USB_CTRL);
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if (enable && usb_pll_valid && usb_pll_enable) {
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ret = -ENODEV;
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/*
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* If the PLL rate has been previously set, then the rate
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* in the PLL register is valid and can be enabled here.
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* Otherwise, it needs to be enabled as part of setrate.
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*/
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/*
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* Gate clock into PLL
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*/
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reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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/* Wait for PLL lock */
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/*
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* Enable PLL
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*/
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reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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/*
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* Wait for PLL to lock
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*/
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while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
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ret = 0;
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else
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udelay(10);
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}
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/*
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* Gate clock from PLL if PLL is locked
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*/
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if (ret == 0) {
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reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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__raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
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LPC32XX_CLKPWR_USB_CTRL);
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} else {
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__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
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LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
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LPC32XX_CLKPWR_USB_CTRL);
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}
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} else if ((enable == 0) && usb_pll_valid && usb_pll_enable) {
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usb_pll_valid = 0;
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usb_pll_enable = 0;
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}
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return ret;
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@ -425,7 +460,7 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
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*/
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rate = rate * 1000;
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clkin = clk->parent->rate;
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clkin = clk->get_rate(clk);
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usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
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LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
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clkin = clkin / usbdiv;
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@ -439,7 +474,8 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
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static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 clkin, reg, usbdiv;
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int ret = -ENODEV;
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u32 clkin, usbdiv;
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struct clk_pll_setup pllsetup;
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/*
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@ -448,7 +484,7 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
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*/
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rate = rate * 1000;
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clkin = clk->get_rate(clk);
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clkin = clk->get_rate(clk->parent);
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usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
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LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
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clkin = clkin / usbdiv;
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@ -457,22 +493,25 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
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if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
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return -EINVAL;
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/*
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* Disable PLL clocks during PLL change
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*/
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local_usbpll_enable(clk, 0);
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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pllsetup.analog_on = 1;
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pllsetup.analog_on = 0;
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local_clk_usbpll_setup(&pllsetup);
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clk->rate = clk_check_pll_setup(clkin, &pllsetup);
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/*
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* Start USB PLL and check PLL status
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*/
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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usb_pll_valid = 1;
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usb_pll_enable = 1;
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return 0;
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ret = local_usbpll_enable(clk, 1);
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if (ret >= 0)
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clk->rate = clk_check_pll_setup(clkin, &pllsetup);
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return ret;
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}
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static struct clk clk_usbpll = {
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@ -159,6 +159,32 @@ struct platform_device lpc32xx_adc_device = {
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.resource = adc_resources,
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};
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/*
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* USB support
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*/
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/* The dmamask must be set for OHCI to work */
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static u64 ohci_dmamask = ~(u32) 0;
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static struct resource ohci_resources[] = {
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{
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.start = IO_ADDRESS(LPC32XX_USB_BASE),
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.end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_LPC32XX_USB_HOST,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device lpc32xx_ohci_device = {
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.name = "usb-ohci",
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.id = -1,
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.dev = {
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.dma_mask = &ohci_dmamask,
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.coherent_dma_mask = 0xFFFFFFFF,
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},
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.num_resources = ARRAY_SIZE(ohci_resources),
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.resource = ohci_resources,
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};
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/*
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* Returns the unique ID for the device
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*/
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@ -31,6 +31,7 @@ extern struct platform_device lpc32xx_i2c2_device;
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extern struct platform_device lpc32xx_tsc_device;
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extern struct platform_device lpc32xx_adc_device;
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extern struct platform_device lpc32xx_rtc_device;
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extern struct platform_device lpc32xx_ohci_device;
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/*
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* Other arch specific structures and functions
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@ -279,6 +279,7 @@ static struct platform_device *phy3250_devs[] __initdata = {
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&lpc32xx_watchdog_device,
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&lpc32xx_gpio_led_device,
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&lpc32xx_adc_device,
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&lpc32xx_ohci_device,
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};
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static struct amba_device *amba_devs[] __initdata = {
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