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drm/radeon/dpm: fix display gap programming on SI

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Need to set the DISP*_GAP fields as well as the
DISP*_GAP_MCHG fields.  Same as on previous asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-07-26 18:05:07 -04:00
parent 7d61d83582
commit 489bc476b4
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/radeon/si_dpm.c
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@ -3620,8 +3620,12 @@ static void si_enable_display_gap(struct radeon_device *rdev)
{ {
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32(CG_DISPLAY_GAP_CNTL, tmp);
} }