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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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firewire: ohci: fix IR/IT context mask mixup
This bug was present in firewire-ohci since day one: The number of available isochronous receive DMA contexts was mixed up with that of available isochronous transmit DMA contexts. This is harmless on a few chips which offer the same number of contexts in both directions, but most chips nowadays implement only the standard minimum of 4 IR contexts, but 8 IT contexts. If a user attempted to run a lot of IR contexts at once, results with more than four were therefore unpredictable. I suppose the controller would simply refuse to start DMA of any unimplemented context. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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parent
3e9cc2f3b7
commit
4802f16d51
@ -2395,18 +2395,18 @@ static int __devinit pci_probe(struct pci_dev *dev,
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OHCI1394_AsRspTrContextControlSet, handle_at_packet);
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reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
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ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
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reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
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size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
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ohci->it_context_list = kzalloc(size, GFP_KERNEL);
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reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
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ohci->ir_context_channels = ~0ULL;
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ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
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reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
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ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
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reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
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size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
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ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
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reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
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ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
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reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
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size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
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ohci->it_context_list = kzalloc(size, GFP_KERNEL);
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if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
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err = -ENOMEM;
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goto fail_contexts;
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