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drm/i915: Compute DSI PLL parameters during .compute_config()

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Compute the DSI PLL parameters during .compute_config() rather than
.pre_pll_enable() so that we can fail gracefully if we can't find
suitable parameters.

In order to do that we need to store the DSI PLL parameters in
pipe_config.

v2: Handle BXT too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460488478-18311-3-git-send-email-ville.syrjala@linux.intel.com
Tested-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2016-04-12 22:14:35 +03:00
parent cd2d34d9b6
commit 47eacbabcb
5 changed files with 114 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/intel_display.c
View File

@ -12763,6 +12763,9 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp); PIPE_CONF_CHECK_I(pipe_bpp);

5
drivers/gpu/drm/i915/intel_drv.h
View File

@ -497,6 +497,11 @@ struct intel_crtc_state {
/* Actual register state of the dpll, for shared dpll cross-checking. */ /* Actual register state of the dpll, for shared dpll cross-checking. */
struct intel_dpll_hw_state dpll_hw_state; struct intel_dpll_hw_state dpll_hw_state;
/* DSI PLL registers */
struct {
u32 ctrl, div;
} dsi_pll;
int pipe_bpp; int pipe_bpp;
struct intel_link_m_n dp_m_n; struct intel_link_m_n dp_m_n;

15
drivers/gpu/drm/i915/intel_dsi.c
View File

@ -292,6 +292,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_connector *intel_connector = intel_dsi->attached_connector; struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int ret;
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
@ -311,10 +312,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->cpu_transcoder = TRANSCODER_DSI_A; pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
} }
/* ret = intel_compute_dsi_pll(encoder, pipe_config);
* FIXME move the DSI PLL calc from vlv_enable_dsi_pll() if (ret)
* to .compute_config(). return false;
*/
pipe_config->clock_set = true; pipe_config->clock_set = true;
return true; return true;
@ -504,6 +505,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev; struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
enum port port; enum port port;
u32 tmp; u32 tmp;
@ -514,7 +516,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
* lock. It needs to be fully powered down to fix it. * lock. It needs to be fully powered down to fix it.
*/ */
intel_disable_dsi_pll(encoder); intel_disable_dsi_pll(encoder);
intel_enable_dsi_pll(encoder); intel_enable_dsi_pll(encoder, crtc->config);
intel_dsi_prepare(encoder); intel_dsi_prepare(encoder);
@ -824,7 +826,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
if (IS_BROXTON(dev)) if (IS_BROXTON(dev))
bxt_dsi_get_pipe_config(encoder, pipe_config); bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
pipe_config);
if (!pclk) if (!pclk)
return; return;

14
drivers/gpu/drm/i915/intel_dsi.h
View File

@ -127,11 +127,15 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
} }
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv); bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
extern void intel_enable_dsi_pll(struct intel_encoder *encoder); int intel_compute_dsi_pll(struct intel_encoder *encoder,
extern void intel_disable_dsi_pll(struct intel_encoder *encoder); struct intel_crtc_state *config);
extern u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp); void intel_enable_dsi_pll(struct intel_encoder *encoder,
extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, const struct intel_crtc_state *config);
enum port port); void intel_disable_dsi_pll(struct intel_encoder *encoder);
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config);
void intel_dsi_reset_clocks(struct intel_encoder *encoder,
enum port port);
struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id); struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);

160
drivers/gpu/drm/i915/intel_dsi_pll.c
View File

@ -30,11 +30,6 @@
#include "i915_drv.h" #include "i915_drv.h"
#include "intel_dsi.h" #include "intel_dsi.h"
struct dsi_mnp {
u32 dsi_pll_ctrl;
u32 dsi_pll_div;
};
static const u16 lfsr_converts[] = { static const u16 lfsr_converts[] = {
426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
@ -57,7 +52,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
} }
static int dsi_calc_mnp(struct drm_i915_private *dev_priv, static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
struct dsi_mnp *dsi_mnp, int target_dsi_clk) struct intel_crtc_state *config,
int target_dsi_clk)
{ {
unsigned int calc_m = 0, calc_p = 0; unsigned int calc_m = 0, calc_p = 0;
unsigned int m_min, m_max, p_min = 2, p_max = 6; unsigned int m_min, m_max, p_min = 2, p_max = 6;
@ -103,8 +99,8 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
/* register has log2(N1), this works fine for powers of two */ /* register has log2(N1), this works fine for powers of two */
n = ffs(n) - 1; n = ffs(n) - 1;
m_seed = lfsr_converts[calc_m - 62]; m_seed = lfsr_converts[calc_m - 62];
dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT |
m_seed << DSI_PLL_M1_DIV_SHIFT; m_seed << DSI_PLL_M1_DIV_SHIFT;
return 0; return 0;
@ -114,54 +110,63 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
* XXX: The muxing and gating is hard coded for now. Need to add support for * XXX: The muxing and gating is hard coded for now. Need to add support for
* sharing PLLs with two DSI outputs. * sharing PLLs with two DSI outputs.
*/ */
static void vlv_configure_dsi_pll(struct intel_encoder *encoder) static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int ret; int ret;
struct dsi_mnp dsi_mnp;
u32 dsi_clk; u32 dsi_clk;
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count); intel_dsi->lane_count);
ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
if (ret) { if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
return; return ret;
} }
if (intel_dsi->ports & (1 << PORT_A)) if (intel_dsi->ports & (1 << PORT_A))
dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
if (intel_dsi->ports & (1 << PORT_C)) if (intel_dsi->ports & (1 << PORT_C))
dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); config->dsi_pll.div, config->dsi_pll.ctrl);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); return 0;
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
} }
static void vlv_enable_dsi_pll(struct intel_encoder *encoder) static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp;
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
}
static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
vlv_configure_dsi_pll(encoder); vlv_configure_dsi_pll(encoder, config);
/* wait at least 0.5 us after ungating before enabling VCO */ /* wait at least 0.5 us after ungating before enabling VCO */
usleep_range(1, 10); usleep_range(1, 10);
tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
tmp |= DSI_PLL_VCO_EN;
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
DSI_PLL_LOCK, 20)) { DSI_PLL_LOCK, 20)) {
@ -177,7 +182,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
static void vlv_disable_dsi_pll(struct intel_encoder *encoder) static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp; u32 tmp;
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
@ -224,7 +229,7 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
static void bxt_disable_dsi_pll(struct intel_encoder *encoder) static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 val; u32 val;
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
@ -251,9 +256,10 @@ static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
bpp, pipe_bpp); bpp, pipe_bpp);
} }
static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 dsi_clock, pclk; u32 dsi_clock, pclk;
u32 pll_ctl, pll_div; u32 pll_ctl, pll_div;
@ -268,6 +274,9 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
mutex_unlock(&dev_priv->sb_lock); mutex_unlock(&dev_priv->sb_lock);
config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
config->dsi_pll.div = pll_div;
/* mask out other bits and extract the P1 divisor */ /* mask out other bits and extract the P1 divisor */
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
@ -313,7 +322,8 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk; return pclk;
} }
static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{ {
u32 pclk; u32 pclk;
u32 dsi_clk; u32 dsi_clk;
@ -327,15 +337,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return 0; return 0;
} }
dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
BXT_DSI_PLL_RATIO_MASK;
/* Invalid DSI ratio ? */ dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
return 0;
}
dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
@ -348,12 +352,13 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk; return pclk;
} }
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{ {
if (IS_BROXTON(encoder->base.dev)) if (IS_BROXTON(encoder->base.dev))
return bxt_dsi_get_pclk(encoder, pipe_bpp); return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else else
return vlv_dsi_get_pclk(encoder, pipe_bpp); return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
} }
static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
@ -370,7 +375,8 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
} }
/* Program BXT Mipi clocks and dividers */ /* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
const struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 tmp; u32 tmp;
@ -390,8 +396,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
/* Get the current DSI rate(actual) */ /* Get the current DSI rate(actual) */
pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
BXT_DSI_PLL_RATIO_MASK;
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
/* /*
@ -427,16 +432,15 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
} }
static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u8 dsi_ratio; u8 dsi_ratio;
u32 dsi_clk; u32 dsi_clk;
u32 val;
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count); intel_dsi->lane_count);
/* /*
* From clock diagram, to get PLL ratio divider, divide double of DSI * From clock diagram, to get PLL ratio divider, divide double of DSI
@ -445,9 +449,9 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
*/ */
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
return false; return -ECHRNG;
} }
/* /*
@ -455,27 +459,28 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
* Spec says both have to be programmed, even if one is not getting * Spec says both have to be programmed, even if one is not getting
* used. Configure MIPI_CLOCK_CTL dividers in modeset * used. Configure MIPI_CLOCK_CTL dividers in modeset
*/ */
val = I915_READ(BXT_DSI_PLL_CTL); config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
val &= ~BXT_DSI_FREQ_SEL_MASK;
val &= ~BXT_DSI_PLL_RATIO_MASK;
val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
/* As per recommendation from hardware team, /* As per recommendation from hardware team,
* Prog PVD ratio =1 if dsi ratio <= 50 * Prog PVD ratio =1 if dsi ratio <= 50
*/ */
if (dsi_ratio <= 50) { if (dsi_ratio <= 50)
val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
val |= BXT_DSI_PLL_PVD_RATIO_1;
}
I915_WRITE(BXT_DSI_PLL_CTL, val); return 0;
POSTING_READ(BXT_DSI_PLL_CTL);
return true;
} }
static void bxt_enable_dsi_pll(struct intel_encoder *encoder) static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
POSTING_READ(BXT_DSI_PLL_CTL);
}
static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@ -485,14 +490,11 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
/* Configure PLL vales */ /* Configure PLL vales */
if (!bxt_configure_dsi_pll(encoder)) { bxt_configure_dsi_pll(encoder, config);
DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
return;
}
/* Program TX, RX, Dphy clocks */ /* Program TX, RX, Dphy clocks */
for_each_dsi_port(port, intel_dsi->ports) for_each_dsi_port(port, intel_dsi->ports)
bxt_dsi_program_clocks(encoder->base.dev, port); bxt_dsi_program_clocks(encoder->base.dev, port, config);
/* Enable DSI PLL */ /* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE); val = I915_READ(BXT_DSI_PLL_ENABLE);
@ -518,14 +520,28 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
return false; return false;
} }
void intel_enable_dsi_pll(struct intel_encoder *encoder) int intel_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{ {
struct drm_device *dev = encoder->base.dev; struct drm_device *dev = encoder->base.dev;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
vlv_enable_dsi_pll(encoder); return vlv_compute_dsi_pll(encoder, config);
else if (IS_BROXTON(dev)) else if (IS_BROXTON(dev))
bxt_enable_dsi_pll(encoder); return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
}
void intel_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
struct drm_device *dev = encoder->base.dev;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
vlv_enable_dsi_pll(encoder, config);
else if (IS_BROXTON(dev))
bxt_enable_dsi_pll(encoder, config);
} }
void intel_disable_dsi_pll(struct intel_encoder *encoder) void intel_disable_dsi_pll(struct intel_encoder *encoder)