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ARM: dts: owl-s500: Add RoseapplePi

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Add a Device Tree for the RoseapplePi SBC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Cristian Ciocaltea 2020-08-28 16:53:20 +03:00 committed by Manivannan Sadhasivam
parent 55f6c9931f
commit 47be1cdee7
2 changed files with 48 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -869,6 +869,7 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-cubieboard6.dtb \
owl-s500-guitar-bb-rev-b.dtb \
owl-s500-labrador-base-m.dtb \
owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb

47
arch/arm/boot/dts/owl-s500-roseapplepi.dts Normal file
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@ -0,0 +1,47 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Roseapple Pi
*
* Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
*/
/dts-v1/;
#include "owl-s500.dtsi"
/ {
compatible = "roseapplepi,roseapplepi", "actions,s500";
model = "Roseapple Pi";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
uart2_clk: uart2-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&twd_timer {
status = "okay";
};
&timer {
clocks = <&hosc>;
};
&uart2 {
status = "okay";
clocks = <&uart2_clk>;
};