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iio: 104-quad-8: Fix index control configuration

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The LS7266R1 requires bits 5 & 6 to be high in order to select the Index
Control Register. This patch fixes a typo that incorrectly selects the
Input/Output Control Register where the Index Control Register was
desired.

Fixes: 28e5d3bb03 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8")
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
William Breathitt Gray 2016-11-28 16:22:44 -05:00 committed by Jonathan Cameron
parent af8bc2fb99
commit 47af2c676a
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/counter/104-quad-8.c
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@ -362,7 +362,7 @@ static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
priv->synchronous_mode[chan->channel] = synchronous_mode;
/* Load Index Control configuration to Index Control Register */
outb(0x40 | idr_cfg, base_offset);
outb(0x60 | idr_cfg, base_offset);
return 0;
}
@ -444,7 +444,7 @@ static int quad8_set_index_polarity(struct iio_dev *indio_dev,
priv->index_polarity[chan->channel] = index_polarity;
/* Load Index Control configuration to Index Control Register */
outb(0x40 | idr_cfg, base_offset);
outb(0x60 | idr_cfg, base_offset);
return 0;
}