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net: dsa: mv88e6xxx: add cap for MGMT Enables bits
Some switches provide a Rsvd2CPU mechanism used to choose which of the
16 reserved multicast destination addresses matching 01:80:c2:00:00:0x
should be considered as MGMT and thus forwarded to the CPU port.
Other switches extend this mechanism to also configure as MGMT the
additional 16 reserved multicast addresses matching 01:80:c2:00:00:2x.
This mechanism is exposed via two registers in Global 2, and an Rsvd2CPU
enable bit in the management register.
Newer chip (such as 88E6390) has replaced these registers with a new
indirect MGMT mechanism in Global 1.
The patch adds two MV88E6XXX_FLAG_G2_MGMT_EN_{0,2}X flags to describe
the presence of these Global 2 registers. If 88E6390 support is added, a
MV88E6XXX_FLAG_G1_MGMT_CTRL flag will be needed to setup Rsvd2CPU.
Note: all switches still support in parallel the ATU Load operation with
an MGMT Entry State to forward such frames in a less convenient way.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
parent
5154041fa7
commit
47395ed280
@ -3196,25 +3196,40 @@ static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
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static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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{
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u16 reg;
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int err;
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int i;
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:0x to the CPU port.
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*/
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err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
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0xffff);
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if (err)
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return err;
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
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/* Consider the frames with reserved multicast destination
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* addresses matching 01:80:c2:00:00:2x as MGMT.
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*/
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
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0xffff);
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if (err)
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return err;
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}
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
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/* Consider the frames with reserved multicast destination
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* addresses matching 01:80:c2:00:00:0x as MGMT.
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*/
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
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0xffff);
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if (err)
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return err;
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}
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/* Ignore removed tag data on doubly tagged packets, disable
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* flow control messages, force flow control priority to the
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* highest, and send all special multicast frames to the CPU
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* port at the highest priority.
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*/
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err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
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0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
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GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
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reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
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mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
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reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
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if (err)
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return err;
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@ -3231,14 +3246,6 @@ static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
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mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
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mv88e6xxx_6320_family(chip)) {
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:2x to the CPU port.
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*/
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err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
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GLOBAL2_MGMT_EN_2X, 0xffff);
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if (err)
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return err;
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/* Initialise cross-chip port VLAN table to reset
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* defaults.
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*/
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@ -388,6 +388,8 @@ enum mv88e6xxx_cap {
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* The device contains a second set of global 16-bit registers.
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*/
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MV88E6XXX_CAP_GLOBAL2,
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MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
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MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
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/* Multi-chip Addressing Mode.
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* Some chips require an indirect SMI access when their SMI device
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@ -436,6 +438,8 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_EEE BIT(MV88E6XXX_CAP_EEE)
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#define MV88E6XXX_FLAG_EEPROM BIT(MV88E6XXX_CAP_EEPROM)
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#define MV88E6XXX_FLAG_GLOBAL2 BIT(MV88E6XXX_CAP_GLOBAL2)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X)
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#define MV88E6XXX_FLAG_MULTI_CHIP BIT(MV88E6XXX_CAP_MULTI_CHIP)
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#define MV88E6XXX_FLAG_PPU BIT(MV88E6XXX_CAP_PPU)
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#define MV88E6XXX_FLAG_PPU_ACTIVE BIT(MV88E6XXX_CAP_PPU_ACTIVE)
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@ -448,12 +452,15 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAGS_FAMILY_6095 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_VTU)
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#define MV88E6XXX_FLAGS_FAMILY_6097 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_STU | \
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@ -461,6 +468,8 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAGS_FAMILY_6165 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_SWITCH_MAC | \
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@ -469,6 +478,7 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAGS_FAMILY_6185 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_VTU)
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@ -477,6 +487,8 @@ enum mv88e6xxx_cap {
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(MV88E6XXX_FLAG_EEE | \
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MV88E6XXX_FLAG_EEPROM | \
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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@ -487,6 +499,8 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAGS_FAMILY_6351 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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@ -499,6 +513,8 @@ enum mv88e6xxx_cap {
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(MV88E6XXX_FLAG_EEE | \
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MV88E6XXX_FLAG_EEPROM | \
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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