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drm/amd/display: clean up dccg divider calc and dcn constructor
No functional change. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
Alex Deucher
parent
12c3130dd6
commit
472800a0a0
@ -101,90 +101,42 @@ static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
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/* Starting point for each divider range.*/
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enum dce_divider_range_start {
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DIVIDER_RANGE_01_START = 200, /* 2.00*/
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DIVIDER_RANGE_02_START = 1600, /* 16.00*/
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DIVIDER_RANGE_03_START = 3200, /* 32.00*/
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DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
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/* Starting DID for each range */
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enum dentist_base_divider_id {
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dentist_base_divider_id_1 = 0x08,
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dentist_base_divider_id_2 = 0x40,
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dentist_base_divider_id_3 = 0x60,
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dentist_max_divider_id = 0x80
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};
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/* Ranges for divider identifiers (Divider ID or DID)
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mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
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enum dce_divider_id_register_setting {
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DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
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DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
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DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
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DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
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/* Starting point and step size for each divider range.*/
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enum dentist_divider_range {
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dentist_divider_range_1_start = 8, /* 2.00 */
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dentist_divider_range_1_step = 1, /* 0.25 */
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dentist_divider_range_2_start = 64, /* 16.00 */
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dentist_divider_range_2_step = 2, /* 0.50 */
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dentist_divider_range_3_start = 128, /* 32.00 */
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dentist_divider_range_3_step = 4, /* 1.00 */
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dentist_divider_range_scale_factor = 4
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};
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/* Step size between each divider within a range.
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Incrementing the DENTIST_DISPCLK_WDIVIDER by one
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will increment the divider by this much.*/
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enum dce_divider_range_step_size {
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DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
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DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
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DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
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};
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static bool dce_divider_range_construct(
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struct dce_divider_range *div_range,
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int range_start,
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int range_step,
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int did_min,
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int did_max)
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static int dentist_get_divider_from_did(int did)
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{
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div_range->div_range_start = range_start;
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div_range->div_range_step = range_step;
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div_range->did_min = did_min;
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div_range->did_max = did_max;
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if (did < dentist_base_divider_id_1)
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did = dentist_base_divider_id_1;
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if (did > dentist_max_divider_id)
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did = dentist_max_divider_id;
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if (div_range->div_range_step == 0) {
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div_range->div_range_step = 1;
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/*div_range_step cannot be zero*/
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BREAK_TO_DEBUGGER();
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if (did < dentist_base_divider_id_2) {
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return dentist_divider_range_1_start + dentist_divider_range_1_step
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* (did - dentist_base_divider_id_1);
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} else if (did < dentist_base_divider_id_3) {
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return dentist_divider_range_2_start + dentist_divider_range_2_step
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* (did - dentist_base_divider_id_2);
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} else {
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return dentist_divider_range_3_start + dentist_divider_range_3_step
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* (did - dentist_base_divider_id_3);
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}
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/* Calculate this based on the other inputs.*/
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/* See DividerRange.h for explanation of */
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/* the relationship between divider id (DID) and a divider.*/
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/* Number of Divider IDs = (Maximum Divider ID - Minimum Divider ID)*/
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/* Maximum divider identified in this range =
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* (Number of Divider IDs)*Step size between dividers
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* + The start of this range.*/
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div_range->div_range_end = (did_max - did_min) * range_step
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+ range_start;
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return true;
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}
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static int dce_divider_range_calc_divider(
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struct dce_divider_range *div_range,
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int did)
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{
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/* Is this DID within our range?*/
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if ((did < div_range->did_min) || (did >= div_range->did_max))
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return INVALID_DIVIDER;
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return ((did - div_range->did_min) * div_range->div_range_step)
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+ div_range->div_range_start;
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}
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static int dce_divider_range_get_divider(
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struct dce_divider_range *div_range,
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int ranges_num,
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int did)
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{
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int div = INVALID_DIVIDER;
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int i;
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for (i = 0; i < ranges_num; i++) {
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/* Calculate divider with given divider ID*/
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div = dce_divider_range_calc_divider(&div_range[i], did);
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/* Found a valid return divider*/
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if (div != INVALID_DIVIDER)
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break;
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}
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return div;
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}
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static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
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@ -193,7 +145,7 @@ static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
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int dprefclk_wdivider;
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int dprefclk_src_sel;
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int dp_ref_clk_khz = 600000;
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int target_div = INVALID_DIVIDER;
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int target_div;
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/* ASSERT DP Reference Clock source is from DFS*/
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REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
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@ -204,16 +156,11 @@ static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
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REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
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/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
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target_div = dce_divider_range_get_divider(
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clk_dce->divider_ranges,
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DIVIDER_RANGE_MAX,
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dprefclk_wdivider);
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target_div = dentist_get_divider_from_did(dprefclk_wdivider);
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if (target_div != INVALID_DIVIDER) {
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/* Calculate the current DFS clock, in kHz.*/
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dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
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dp_ref_clk_khz = (dentist_divider_range_scale_factor
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* clk_dce->dentist_vco_freq_khz) / target_div;
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}
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/* SW will adjust DP REF Clock average value for all purposes
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* (DP DTO / DP Audio DTO and DP GTC)
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@ -229,17 +176,12 @@ static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
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*/
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if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
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struct fixed31_32 ss_percentage = dc_fixpt_div_int(
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dc_fixpt_from_fraction(
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clk_dce->dprefclk_ss_percentage,
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dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,
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clk_dce->dprefclk_ss_divider), 200);
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struct fixed31_32 adj_dp_ref_clk_khz;
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ss_percentage = dc_fixpt_sub(dc_fixpt_one,
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ss_percentage);
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adj_dp_ref_clk_khz =
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dc_fixpt_mul_int(
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ss_percentage,
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dp_ref_clk_khz);
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ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
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adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
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dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
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}
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@ -257,17 +199,12 @@ static int dce_clocks_get_dp_ref_freq_wrkaround(struct dccg *clk)
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if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
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struct fixed31_32 ss_percentage = dc_fixpt_div_int(
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dc_fixpt_from_fraction(
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clk_dce->dprefclk_ss_percentage,
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dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,
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clk_dce->dprefclk_ss_divider), 200);
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struct fixed31_32 adj_dp_ref_clk_khz;
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ss_percentage = dc_fixpt_sub(dc_fixpt_one,
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ss_percentage);
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adj_dp_ref_clk_khz =
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dc_fixpt_mul_int(
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ss_percentage,
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dp_ref_clk_khz);
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ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
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adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
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dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
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}
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@ -804,25 +741,6 @@ static void dce_dccg_construct(
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dce_clock_read_integrated_info(clk_dce);
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dce_clock_read_ss_info(clk_dce);
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dce_divider_range_construct(
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&clk_dce->divider_ranges[DIVIDER_RANGE_01],
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DIVIDER_RANGE_01_START,
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DIVIDER_RANGE_01_STEP_SIZE,
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DIVIDER_RANGE_01_BASE_DIVIDER_ID,
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DIVIDER_RANGE_02_BASE_DIVIDER_ID);
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dce_divider_range_construct(
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&clk_dce->divider_ranges[DIVIDER_RANGE_02],
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DIVIDER_RANGE_02_START,
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DIVIDER_RANGE_02_STEP_SIZE,
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DIVIDER_RANGE_02_BASE_DIVIDER_ID,
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DIVIDER_RANGE_03_BASE_DIVIDER_ID);
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dce_divider_range_construct(
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&clk_dce->divider_ranges[DIVIDER_RANGE_03],
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DIVIDER_RANGE_03_START,
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DIVIDER_RANGE_03_STEP_SIZE,
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DIVIDER_RANGE_03_BASE_DIVIDER_ID,
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DIVIDER_RANGE_MAX_DIVIDER_ID);
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}
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struct dccg *dce_dccg_create(
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@ -921,6 +839,9 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
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struct dccg *dcn1_dccg_create(struct dc_context *ctx)
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{
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struct dc_debug *debug = &ctx->dc->debug;
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struct dc_bios *bp = ctx->dc_bios;
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struct dc_firmware_info fw_info = { { 0 } };
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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if (clk_dce == NULL) {
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@ -928,12 +849,30 @@ struct dccg *dcn1_dccg_create(struct dc_context *ctx)
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return NULL;
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}
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/* TODO strip out useful stuff out of dce constructor */
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dce_dccg_construct(
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clk_dce, ctx, NULL, NULL, NULL);
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clk_dce->base.ctx = ctx;
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clk_dce->base.funcs = &dcn1_funcs;
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clk_dce->dfs_bypass_disp_clk = 0;
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clk_dce->dprefclk_ss_percentage = 0;
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clk_dce->dprefclk_ss_divider = 1000;
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clk_dce->ss_on_dprefclk = false;
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if (bp->integrated_info)
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clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (clk_dce->dentist_vco_freq_khz == 0) {
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bp->funcs->get_firmware_info(bp, &fw_info);
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clk_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
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if (clk_dce->dentist_vco_freq_khz == 0)
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clk_dce->dentist_vco_freq_khz = 3600000;
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}
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if (!debug->disable_dfs_bypass && bp->integrated_info)
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if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
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clk_dce->dfs_bypass_enabled = true;
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dce_clock_read_ss_info(clk_dce);
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return &clk_dce->base;
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}
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@ -57,31 +57,6 @@ struct dce_disp_clk_registers {
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uint32_t DENTIST_DISPCLK_CNTL;
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};
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/* Array identifiers and count for the divider ranges.*/
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enum dce_divider_range_count {
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DIVIDER_RANGE_01 = 0,
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DIVIDER_RANGE_02,
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DIVIDER_RANGE_03,
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DIVIDER_RANGE_MAX /* == 3*/
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};
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enum dce_divider_error_types {
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INVALID_DID = 0,
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INVALID_DIVIDER = 1
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};
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struct dce_divider_range {
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int div_range_start;
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/* The end of this range of dividers.*/
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int div_range_end;
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/* The distance between each divider in this range.*/
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int div_range_step;
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/* The divider id for the lowest divider.*/
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int did_min;
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/* The divider id for the highest divider.*/
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int did_max;
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};
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struct dce_dccg {
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struct dccg base;
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const struct dce_disp_clk_registers *regs;
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@ -89,7 +64,6 @@ struct dce_dccg {
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const struct dce_disp_clk_mask *clk_mask;
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struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
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struct dce_divider_range divider_ranges[DIVIDER_RANGE_MAX];
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int dentist_vco_freq_khz;
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