mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 21:30:54 +07:00
ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields
Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The OMAP4430 Public TRM vV has these fields mentioned correctly. Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
be73246058
commit
46f8c3c7e9
@ -941,10 +941,10 @@
|
||||
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
|
||||
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
|
||||
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
|
||||
#define OMAP4_DSI1_PIPD_SHIFT 19
|
||||
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
|
||||
#define OMAP4_DSI2_PIPD_SHIFT 14
|
||||
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
|
||||
#define OMAP4_DSI2_PIPD_SHIFT 19
|
||||
#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
|
||||
#define OMAP4_DSI1_PIPD_SHIFT 14
|
||||
#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
|
||||
|
||||
/* CONTROL_MCBSPLP */
|
||||
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
|
||||
|
Loading…
Reference in New Issue
Block a user