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drm/i915: use proper FBC base register on all new platforms

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Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.

Motivated by Rodrigo's request to check FBC support on BXT.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak 2015-03-26 17:35:40 +02:00 committed by Daniel Vetter
parent ce89db2eab
commit 46ec15f266
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/i915_gem_stolen.c
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@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
dev_priv->fbc.threshold = ret; dev_priv->fbc.threshold = ret;
if (HAS_PCH_SPLIT(dev)) if (INTEL_INFO(dev_priv)->gen >= 5)
I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
else if (IS_GM45(dev)) { else if (IS_GM45(dev)) {
I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);