arm64: dts: meson: fix PHY deassert timing requirements

[ Upstream commit c183c406c4321002fe85b345b51bc1a3a04b6d33 ]

According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. This fixes an issue seen on ODROID-C2 where the Ethernet
link doesn't come up when using ip link set down/up:
  [ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down
  [ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36)
  [ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma
  [ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
  [ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed

Fixes: f29cabf240 ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings")
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Stefan Agner 2020-12-07 18:58:00 +01:00 committed by Greg Kroah-Hartman
parent a83bf12907
commit 46b7f22498
9 changed files with 9 additions and 9 deletions

View File

@ -165,7 +165,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

View File

@ -200,7 +200,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

View File

@ -126,7 +126,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

View File

@ -147,7 +147,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

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@ -82,7 +82,7 @@ external_phy: ethernet-phy@0 {
/* External PHY reset is shared with internal PHY Led signal */ /* External PHY reset is shared with internal PHY Led signal */
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

View File

@ -194,7 +194,7 @@ external_phy: ethernet-phy@0 {
reg = <0>; reg = <0>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

View File

@ -112,7 +112,7 @@ external_phy: ethernet-phy@0 {
max-speed = <1000>; max-speed = <1000>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
}; };
}; };

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@ -64,7 +64,7 @@ external_phy: ethernet-phy@0 {
/* External PHY reset is shared with internal PHY Led signal */ /* External PHY reset is shared with internal PHY Led signal */
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;

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@ -114,7 +114,7 @@ external_phy: ethernet-phy@0 {
max-speed = <1000>; max-speed = <1000>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
reset-deassert-us = <30000>; reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
}; };
}; };