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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-19 06:07:22 +07:00
powerpc/powernv: Move npu struct from pnv_phb to pci_controller
The powernv PCI code stores NPU data in the pnv_phb struct. The latter is referenced by pci_controller::private_data. We are going to have NPU2 support in the pseries platform as well but it does not store any private_data in in the pci_controller struct; and even if it did, it would be a different data structure. This makes npu a pointer and stores it one level higher in the pci_controller struct. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Alexey Kardashevskiy
Michael Ellerman
parent
c10c21efa4
commit
46a1449d9e
@ -129,6 +129,7 @@ struct pci_controller {
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#endif /* CONFIG_PPC64 */
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void *private_data;
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struct npu *npu;
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};
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/* These are used for config access before all the PCI probing
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@ -326,6 +326,25 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
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return gpe;
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}
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/*
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* NPU2 ATS
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*/
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/* Maximum possible number of ATSD MMIO registers per NPU */
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#define NV_NMMU_ATSD_REGS 8
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/* An NPU descriptor, valid for POWER9 only */
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struct npu {
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int index;
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__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
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unsigned int mmio_atsd_count;
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/* Bitmask for MMIO register usage */
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unsigned long mmio_atsd_usage;
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/* Do we need to explicitly flush the nest mmu? */
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bool nmmu_flush;
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};
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/* Maximum number of nvlinks per npu */
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#define NV_MAX_LINKS 6
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@ -477,7 +496,6 @@ static void acquire_atsd_reg(struct npu_context *npu_context,
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int i, j;
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struct npu *npu;
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struct pci_dev *npdev;
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struct pnv_phb *nphb;
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for (i = 0; i <= max_npu2_index; i++) {
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mmio_atsd_reg[i].reg = -1;
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@ -492,8 +510,7 @@ static void acquire_atsd_reg(struct npu_context *npu_context,
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if (!npdev)
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continue;
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nphb = pci_bus_to_host(npdev->bus)->private_data;
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npu = &nphb->npu;
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npu = pci_bus_to_host(npdev->bus)->npu;
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mmio_atsd_reg[i].npu = npu;
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mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
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while (mmio_atsd_reg[i].reg < 0) {
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@ -661,6 +678,7 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
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struct pnv_phb *nphb;
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struct npu *npu;
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struct npu_context *npu_context;
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struct pci_controller *hose;
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/*
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* At present we don't support GPUs connected to multiple NPUs and I'm
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@ -688,8 +706,9 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
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return ERR_PTR(-EINVAL);
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}
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nphb = pci_bus_to_host(npdev->bus)->private_data;
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npu = &nphb->npu;
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hose = pci_bus_to_host(npdev->bus);
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nphb = hose->private_data;
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npu = hose->npu;
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/*
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* Setup the NPU context table for a particular GPU. These need to be
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@ -763,7 +782,7 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
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*/
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WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
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if (!nphb->npu.nmmu_flush) {
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if (!npu->nmmu_flush) {
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/*
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* If we're not explicitly flushing ourselves we need to mark
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* the thread for global flushes
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@ -801,6 +820,7 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
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struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
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struct device_node *nvlink_dn;
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u32 nvlink_index;
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struct pci_controller *hose;
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if (WARN_ON(!npdev))
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return;
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@ -808,8 +828,9 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
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if (!firmware_has_feature(FW_FEATURE_OPAL))
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return;
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nphb = pci_bus_to_host(npdev->bus)->private_data;
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npu = &nphb->npu;
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hose = pci_bus_to_host(npdev->bus);
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nphb = hose->private_data;
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npu = hose->npu;
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nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
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if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
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&nvlink_index)))
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@ -887,9 +908,15 @@ int pnv_npu2_init(struct pnv_phb *phb)
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struct pci_dev *gpdev;
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static int npu_index;
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uint64_t rc = 0;
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struct pci_controller *hose = phb->hose;
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struct npu *npu;
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int ret;
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phb->npu.nmmu_flush =
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of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
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npu = kzalloc(sizeof(*npu), GFP_KERNEL);
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if (!npu)
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return -ENOMEM;
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npu->nmmu_flush = of_property_read_bool(hose->dn, "ibm,nmmu-flush");
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for_each_child_of_node(phb->hose->dn, dn) {
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gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
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if (gpdev) {
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@ -903,18 +930,29 @@ int pnv_npu2_init(struct pnv_phb *phb)
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}
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}
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for (i = 0; !of_property_read_u64_index(phb->hose->dn, "ibm,mmio-atsd",
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for (i = 0; !of_property_read_u64_index(hose->dn, "ibm,mmio-atsd",
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i, &mmio_atsd); i++)
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phb->npu.mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
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npu->mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
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pr_info("NPU%lld: Found %d MMIO ATSD registers", phb->opal_id, i);
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phb->npu.mmio_atsd_count = i;
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phb->npu.mmio_atsd_usage = 0;
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pr_info("NPU%d: Found %d MMIO ATSD registers", hose->global_number, i);
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npu->mmio_atsd_count = i;
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npu->mmio_atsd_usage = 0;
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npu_index++;
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if (WARN_ON(npu_index >= NV_MAX_NPUS))
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return -ENOSPC;
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if (WARN_ON(npu_index >= NV_MAX_NPUS)) {
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ret = -ENOSPC;
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goto fail_exit;
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}
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max_npu2_index = npu_index;
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phb->npu.index = npu_index;
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npu->index = npu_index;
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hose->npu = npu;
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return 0;
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fail_exit:
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for (i = 0; i < npu->mmio_atsd_count; ++i)
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iounmap(npu->mmio_atsd_regs[i]);
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kfree(npu);
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return ret;
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}
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@ -1278,7 +1278,7 @@ static void pnv_pci_ioda_setup_PEs(void)
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pnv_ioda_reserve_pe(phb, 0);
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pnv_ioda_setup_npu_PEs(hose->bus);
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if (phb->model == PNV_PHB_MODEL_NPU2)
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pnv_npu2_init(phb);
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WARN_ON_ONCE(pnv_npu2_init(phb));
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}
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if (phb->type == PNV_PHB_NPU_OCAPI) {
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bus = hose->bus;
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@ -8,9 +8,6 @@
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struct pci_dn;
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/* Maximum possible number of ATSD MMIO registers per NPU */
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#define NV_NMMU_ATSD_REGS 8
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enum pnv_phb_type {
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PNV_PHB_IODA1 = 0,
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PNV_PHB_IODA2 = 1,
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@ -174,19 +171,6 @@ struct pnv_phb {
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unsigned int diag_data_size;
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u8 *diag_data;
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/* Nvlink2 data */
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struct npu {
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int index;
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__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
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unsigned int mmio_atsd_count;
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/* Bitmask for MMIO register usage */
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unsigned long mmio_atsd_usage;
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/* Do we need to explicitly flush the nest mmu? */
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bool nmmu_flush;
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} npu;
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int p2p_target_count;
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};
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