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mISDN: Order IPAC register defines
It looks like IPAC/ISAC chips register defines weren't in any particular order. Order them by their number to make it easier to spot holes. Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Acked-by: Karsten Keil <keil@b1-systems.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -99,32 +99,32 @@ struct ipac_hw {
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/* All registers original Siemens Spec */
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/* IPAC/ISAC registers */
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#define ISAC_MASK 0x20
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#define ISAC_ISTA 0x20
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#define ISAC_STAR 0x21
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#define ISAC_MASK 0x20
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#define ISAC_CMDR 0x21
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#define ISAC_STAR 0x21
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#define ISAC_MODE 0x22
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#define ISAC_TIMR 0x23
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#define ISAC_EXIR 0x24
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#define ISAC_ADF2 0x39
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#define ISAC_RBCL 0x25
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#define ISAC_RSTA 0x27
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#define ISAC_RBCH 0x2A
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#define ISAC_SPCR 0x30
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#define ISAC_ADF1 0x38
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#define ISAC_CIR0 0x31
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#define ISAC_CIX0 0x31
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#define ISAC_CIR1 0x33
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#define ISAC_CIX1 0x33
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#define ISAC_STCR 0x37
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#define ISAC_MODE 0x22
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#define ISAC_RSTA 0x27
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#define ISAC_RBCL 0x25
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#define ISAC_RBCH 0x2A
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#define ISAC_TIMR 0x23
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#define ISAC_SQXR 0x3b
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#define ISAC_SQRR 0x3b
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#define ISAC_MOSR 0x3a
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#define ISAC_MOCR 0x3a
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#define ISAC_MOR0 0x32
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#define ISAC_MOX0 0x32
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#define ISAC_CIR1 0x33
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#define ISAC_CIX1 0x33
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#define ISAC_MOR1 0x34
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#define ISAC_MOX1 0x34
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#define ISAC_STCR 0x37
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#define ISAC_ADF1 0x38
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#define ISAC_ADF2 0x39
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#define ISAC_MOCR 0x3a
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#define ISAC_MOSR 0x3a
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#define ISAC_SQRR 0x3b
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#define ISAC_SQXR 0x3b
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#define ISAC_RBCH_XAC 0x80
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@ -212,13 +212,13 @@ struct ipac_hw {
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#define ISAC_CMD_DUI 0xF
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/* ISAC/ISACX/IPAC/IPACX L1 indications */
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#define ISAC_IND_RS 0x1
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#define ISAC_IND_PU 0x7
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#define ISAC_IND_DR 0x0
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#define ISAC_IND_RS 0x1
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#define ISAC_IND_SD 0x2
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#define ISAC_IND_DIS 0x3
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#define ISAC_IND_EI 0x6
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#define ISAC_IND_RSY 0x4
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#define ISAC_IND_EI 0x6
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#define ISAC_IND_PU 0x7
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#define ISAC_IND_ARD 0x8
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#define ISAC_IND_TI 0xA
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#define ISAC_IND_ATI 0xB
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@ -339,9 +339,9 @@ struct ipac_hw {
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#define ISACX__AUX 0x08
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#define ISACX__CIC 0x10
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#define ISACX__ST 0x20
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#define IPACX__ON 0x2C
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#define IPACX__ICB 0x40
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#define IPACX__ICA 0x80
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#define IPACX__ON 0x2C
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/* ISACX/IPACX _CMDRD (W) */
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#define ISACX_CMDRD_XRES 0x01
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