mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 18:20:54 +07:00
Part 2 of device tree changes for omaps for v4.6 merge window:
- A series of GPMC related interrupt changes from Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt support to the NAND driver - Add RTC support for ti81xx - Correct LogicPD Torpedo mode description - Add basic support for LG Optimus Black phone in several patches by Paul Kocialkowski <contact@paulk.fr> - Change address-cells for dra7 for LPAE - Add TBCLK for PWMSS on dra7 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW1h3JAAoJEBvUPslcq6Vz3sQQALjoT1HdNXPsS9fxoCBMRvcc ZLMrntfj7QId/uZ63zhSxUqYRZWAGz9paDl43uS6uwWGL7G+Mml8fcpxKR008co2 gKPmAwTIYtfZDq63/mQ38jIkmr4Nj/qvY6COFDz2s5IIv41m2LMEleX5QBs8k/3X F0FL5A9DYRaVZ5tYmZ64mVcJM/CIdDwyRjhtlV1QHVJrDQVPqcRyZGLuRzQKgati HG0rUc8/B4ECEryrDK5ZtNqJ5LmpThfyzrjaUMzA8mOBo5HTAOOAkwFTtAxppba9 mHZQgNrJ+nAOShDmb+1wAanWw9s+UtsjKppbOhNdk2QyP4DCX8WIsRPZtp/aiDN8 6+I9mYspffe+uFKrwOpcWqtUk+Dft4P0rbcWGm5Pp+dbfSa94gYoyzHDByP5Lgtv DOMpEZfqC/uHuhjS3ZIN4EnT2t3mY2aMupWYIWKxjv06X+Cp80XIdB5NVGzGFsqe 5ksvykF75YxMskdyo6egT+2jr+bgRkEs6H76ZHqkc6qTtGxIu6JHiuolOOen8uGH gk3QbWY6oN6uzwtpcddQkrZkYxeoxOIH9AobHuNQ2MlCE0HwCXNE7U79/fjAv9Zs dbwkVo5C0fraNG+f2waFskwni3mkUYiUIs8/YXXPLsXKavs9XvL5Wxxz/u7v5c+/ 0hdZB8mJuoEtKvmhNk8Z =JMzE -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Pull "Part 2 of device tree changes for omaps for v4.6 merge window" from Tony Lindgren: - A series of GPMC related interrupt changes from Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt support to the NAND driver - Add RTC support for ti81xx - Correct LogicPD Torpedo mode description - Add basic support for LG Optimus Black phone in several patches by Paul Kocialkowski <contact@paulk.fr> - Change address-cells for dra7 for LPAE - Add TBCLK for PWMSS on dra7 * tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: omap3-sniper: TWL4030 keypad support Revert "ARM: dts: DRA7: Add dt nodes for PWMSS" ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND ARM: dts: dm814x: dra62x: Fix NAND device nodes ARM: dts: DRA7: Add dt nodes for PWMSS ARM: dts: DRA7: Add TBCLK for PWMSS ARM: dts: DRA7: change address-cells and size-cells ARM: dts: omap3-sniper: USB OTG support ARM: dts: LG Optimus Black codename sniper basic support ARM: dts: dm3730-torpedo-devkit: Add "Wireless" to model ARM: dts: Add RTC entry for dm816x ARM: dts: Add RTC entry for dm814x and dra62x ARM: dts: omap3: Fix NAND device nodes ARM: dts: dm8168-evm: ARM: dts: Disable wait pin monitoring for NAND ARM: dts: dm816x: Fix NAND device nodes ARM: dts: am335x: Disable wait pin monitoring for NAND ARM: dts: am335x: Fix NAND device nodes ARM: dts: am437x: Disable wait pin monitoring for NAND ARM: dts: am437x: Fix NAND device nodes ARM: dts: dra7: Remove redundant nand property ...
This commit is contained in:
Arnd Bergmann
commit
4615b4e0e6
@ -468,6 +468,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
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omap3-sbc-t3517.dtb \
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omap3-sbc-t3530.dtb \
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omap3-sbc-t3730.dtb \
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omap3-sniper.dtb \
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omap3-thunder.dtb \
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omap3-zoom3.dtb
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dtb-$(CONFIG_SOC_TI81XX) += \
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@ -236,7 +236,11 @@ &gpmc {
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status = "okay";
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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ti,nand-xfer-type = "polled";
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@ -257,12 +261,9 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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@ -7,6 +7,7 @@
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* published by the Free Software Foundation.
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*/
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Grinn AM335x ChiliSOM";
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@ -218,7 +219,11 @@ &gpmc {
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -237,12 +242,9 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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};
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@ -406,7 +406,11 @@ &gpmc {
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -425,12 +429,9 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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@ -519,7 +519,11 @@ &gpmc {
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pinctrl-0 = <&nandflash_pins_s0>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -538,12 +542,9 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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cpus {
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@ -129,7 +130,11 @@ &gpmc {
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-width = <1>;
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@ -147,12 +152,9 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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@ -8,6 +8,7 @@
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*/
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Phytec AM335x phyCORE";
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@ -165,7 +166,11 @@ &gpmc {
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
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nandflash: nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-nand = "true";
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@ -184,13 +189,10 @@ nandflash: nand@0,0 {
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gpmc,access-ns = <30>;
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gpmc,rd-cycle-ns = <30>;
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gpmc,wr-cycle-ns = <30>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <50>;
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gpmc,cycle2cycle-diffcsen;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <30>;
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gpmc,wr-data-mux-bus-ns = <0>;
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@ -866,6 +866,8 @@ gpmc: gpmc@50000000 {
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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@ -894,6 +894,8 @@ gpmc: gpmc@50000000 {
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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@ -146,7 +146,11 @@ &gpmc {
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pinctrl-0 = <&nand_flash_x8>;
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ranges = <0 0 0x08000000 0x1000000>;
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nand@0,0 {
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reg = <0 0 0>;
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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@ -166,17 +170,12 @@ nand@0,0 {
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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gpmc,wait-pin = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* MTD partition table */
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@ -810,9 +810,13 @@ &gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x8>;
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ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* device IO registers */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch16";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -831,11 +835,9 @@ nand@0,0 {
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gpmc,access-ns = <30>;
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,wait-pin = <0>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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@ -561,9 +561,13 @@ &gpmc {
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status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x8>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch16";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -582,11 +586,9 @@ nand@0,0 {
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gpmc,access-ns = <30>; /* tCEA + 4*/
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,wait-pin = <0>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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@ -24,7 +24,7 @@ aliases {
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memory {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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vdd_3v3: fixedregulator-vdd_3v3 {
|
||||
|
||||
@ -21,7 +21,7 @@ / {
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
|
||||
reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
|
||||
};
|
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|
||||
leds {
|
||||
|
||||
@ -6,6 +6,7 @@
|
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/dts-v1/;
|
||||
|
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#include "dm814x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DM8148 EVM";
|
||||
@ -39,8 +40,12 @@ &gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
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linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
@ -60,12 +65,9 @@ nand@0,0 {
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
|
||||
@ -305,6 +305,13 @@ mmc1: mmc@60000 {
|
||||
reg = <0x60000 0x1000>;
|
||||
};
|
||||
|
||||
rtc: rtc@c0000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0xc0000 0x1000>;
|
||||
interrupts = <75 76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
mmc2: mmc@1d8000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc2";
|
||||
@ -559,6 +566,8 @@ gpmc: gpmc@50000000 {
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "dm816x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DM8168 EVM";
|
||||
@ -85,8 +86,12 @@ &gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
@ -106,12 +111,9 @@ nand@0,0 {
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
|
||||
@ -183,6 +183,8 @@ gpmc: gpmc@50000000 {
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48028000 {
|
||||
@ -214,6 +216,13 @@ intc: interrupt-controller@48200000 {
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
rtc: rtc@480c0000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0x480c0000 0x1000>;
|
||||
interrupts = <75 76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480c8000 0x2000>;
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra62x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DRA62x J5 Eco EVM";
|
||||
@ -39,8 +40,12 @@ &gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
@ -60,12 +65,9 @@ nand@0,0 {
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
|
||||
@ -18,7 +18,7 @@ / {
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x60000000>; /* 1536 MB */
|
||||
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
|
||||
};
|
||||
|
||||
evm_3v3_sd: fixedregulator-sd {
|
||||
@ -741,9 +741,13 @@ &gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x16>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
@ -766,7 +770,6 @@ nand@0,0 {
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
||||
@ -15,8 +15,8 @@
|
||||
#define MAX_SOURCES 400
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
compatible = "ti,dra7xx";
|
||||
interrupt-parent = <&crossbar_mpu>;
|
||||
@ -57,10 +57,10 @@ gic: interrupt-controller@48211000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48211000 0x1000>,
|
||||
<0x48212000 0x1000>,
|
||||
<0x48214000 0x2000>,
|
||||
<0x48216000 0x2000>;
|
||||
reg = <0x0 0x48211000 0x0 0x1000>,
|
||||
<0x0 0x48212000 0x0 0x1000>,
|
||||
<0x0 0x48214000 0x0 0x2000>,
|
||||
<0x0 0x48216000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
@ -69,7 +69,7 @@ wakeupgen: interrupt-controller@48281000 {
|
||||
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48281000 0x1000>;
|
||||
reg = <0x0 0x48281000 0x0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
@ -96,10 +96,10 @@ ocp {
|
||||
compatible = "ti,dra7-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x0 0x0 0xc0000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2";
|
||||
reg = <0x44000000 0x1000000>,
|
||||
<0x45000000 0x1000>;
|
||||
reg = <0x0 0x44000000 0x0 0x1000000>,
|
||||
<0x0 0x45000000 0x0 0x1000>;
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -1402,6 +1402,8 @@ gpmc: gpmc@50000000 {
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ / {
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1024 MB */
|
||||
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
@ -492,13 +492,17 @@ &gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_default>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
/* To use NAND, DIP switch SW5 must be set like so:
|
||||
* SW5.1 (NAND_SELn) = ON (LOW)
|
||||
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
||||
*/
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
@ -521,7 +525,6 @@ nand@0,0 {
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
||||
@ -2146,4 +2146,28 @@ dss_deshdcp_clk: dss_deshdcp_clk {
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x558>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <20>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <21>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
#include "omap-gpmc-smsc9221.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LogicPD Zoom DM3730 Torpedo Development Kit";
|
||||
model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
|
||||
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
|
||||
|
||||
gpio_keys {
|
||||
@ -102,7 +102,8 @@ &charger {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */
|
||||
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
|
||||
1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */
|
||||
|
||||
ethernet@gpmc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -35,11 +35,15 @@ wl12xx_vmmc: wl12xx_vmmc {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
|
||||
@ -384,8 +384,11 @@ &gpmc {
|
||||
|
||||
/* Chip select 0 */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
|
||||
interrupts = <20>;
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "ham1";
|
||||
nand-bus-width = <16>;
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -261,10 +261,14 @@ &mcbsp2 {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x01000000>;
|
||||
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
ti,nand-ecc-opt = "sw";
|
||||
|
||||
@ -204,7 +204,11 @@ &gpmc {
|
||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
ti,nand-ecc-opt = "sw";
|
||||
|
||||
@ -154,12 +154,16 @@ &uart3 {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
|
||||
ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
|
||||
<5 0 0x2c000000 0x01000000>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "hynix,h8kds0un0mer-4em";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
@ -492,7 +492,11 @@ &gpmc {
|
||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
|
||||
@ -99,8 +99,12 @@ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
|
||||
|
||||
&gpmc {
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,mt29c4g96maz";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
@ -210,8 +210,8 @@ eeprom@50 {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x20000000>,
|
||||
<5 0 0x2c000000 0x01000000>;
|
||||
ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
|
||||
<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
|
||||
|
||||
ethernet@gpmc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -99,3 +99,7 @@ &uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
};
|
||||
|
||||
@ -97,12 +97,16 @@ key_down {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x01000000>,
|
||||
<1 0 0x08000000 0x01000000>;
|
||||
ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */
|
||||
<1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
@ -362,7 +362,11 @@ &gpmc {
|
||||
<7 0 0x15000000 0x01000000>;
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
/* no elm on omap3 */
|
||||
|
||||
@ -226,8 +226,12 @@ &gpmc {
|
||||
ranges = <0 0 0x00000000 0x20000000>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
linux,mtd-name= "micron,mt29c4g96maz";
|
||||
reg = <0 0 0>;
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
@ -546,7 +546,11 @@ &gpmc {
|
||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "sw";
|
||||
|
||||
|
||||
254
arch/arm/boot/dts/omap3-sniper.dts
Normal file
254
arch/arm/boot/dts/omap3-sniper.dts
Normal file
@ -0,0 +1,254 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Paul Kocialkowski <contact@paulk.fr>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap36xx.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "LG Optimus Black";
|
||||
compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vcc>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
|
||||
uart3_pins: pinmux_uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */
|
||||
>;
|
||||
};
|
||||
|
||||
dp3t_sel_pins: pinmux_dp3t_sel_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */
|
||||
OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
|
||||
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c2_pins: pinmux_i2c2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
|
||||
OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins: pinmux_i2c3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
|
||||
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
lp8720_en_pin: pinmux_lp8720_en_pin {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */
|
||||
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */
|
||||
OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */
|
||||
OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */
|
||||
OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */
|
||||
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb_otg_hs_pins: pinmux_usb_otg_hs_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */
|
||||
OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */
|
||||
OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */
|
||||
OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */
|
||||
OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */
|
||||
OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */
|
||||
OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */
|
||||
OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */
|
||||
OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */
|
||||
OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */
|
||||
OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */
|
||||
OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_wkup {
|
||||
pinctrl-names = "default";
|
||||
|
||||
mmc1_cd_pin: pinmux_mmc1_cd_pin {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins &dp3t_sel_pins>;
|
||||
|
||||
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
twl: twl@48 {
|
||||
reg = <0x48>;
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
power {
|
||||
compatible = "ti,twl4030-power";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
lp8720@7d {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lp8720_en_pin>;
|
||||
|
||||
compatible = "ti,lp8720";
|
||||
reg = <0x7d>;
|
||||
|
||||
enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */
|
||||
|
||||
lp8720_ldo1: ldo1 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>;
|
||||
|
||||
vmmc-supply = <&lp8720_ldo1>;
|
||||
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
|
||||
vmmc-supply = <&vmmc2>;
|
||||
ti,non-removable;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_otg_hs {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_hs_pins>;
|
||||
|
||||
interface-type = <0>;
|
||||
usb-phy = <&usb2_phy>;
|
||||
phys = <&usb2_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
mode = <3>;
|
||||
power = <50>;
|
||||
};
|
||||
|
||||
#include "twl4030.dtsi"
|
||||
#include "twl4030_omap3.dtsi"
|
||||
|
||||
&twl_keypad {
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP)
|
||||
MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(0x02, 0x00, KEY_SELECT)
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3.
|
||||
* When not powered, these sensors cause the I2C3 clock to stay low at all times,
|
||||
* making it impossible to reach other devices on I2C3.
|
||||
*/
|
||||
|
||||
&vaux2 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&vdac {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
@ -275,10 +275,14 @@ &mcbsp3 {
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x01000000>;
|
||||
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
|
||||
ti,nand-ecc-opt = "sw";
|
||||
|
||||
@ -723,6 +723,8 @@ gpmc: gpmc@6e000000 {
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
usb_otg_hs: usb_otg_hs@480ab000 {
|
||||
|
||||
@ -103,10 +103,14 @@ partition@280000 {
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,mt29f1g08abb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
|
||||
ti,nand-ecc-opt = "sw";
|
||||
nand-bus-width = <8>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user