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dt-bindings: clk: versaclock5: convert to yaml
Convert to yaml the VersaClock bindings document. The mapping between clock specifier and physical pins cannot be described formally in yaml schema, then keep it verbatim in the description field. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20200723074112.3159-4-luca@lucaceresoli.net Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Luca Ceresoli
Stephen Boyd
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db136ac978
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45c940184b
@ -1,125 +0,0 @@
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Binding for IDT VersaClock 5,6 programmable i2c clock generators.
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The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
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generators providing from 3 to 12 output clocks.
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==I2C device node==
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Required properties:
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- compatible: shall be one of
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"idt,5p49v5923"
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"idt,5p49v5925"
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"idt,5p49v5933"
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"idt,5p49v5935"
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"idt,5p49v6901"
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"idt,5p49v6965"
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- reg: i2c device address, shall be 0x68 or 0x6a.
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: from common clock binding; list of parent clock handles,
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- 5p49v5923 and
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5p49v5925 and
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5p49v6901: (required) either or both of XTAL or CLKIN
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reference clock.
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present (internal
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Xtal used) or CLKIN reference
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clock.
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- clock-names: from common clock binding; clock input names, can be
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- 5p49v5923 and
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5p49v5925 and
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5p49v6901: (required) either or both of "xin", "clkin".
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present or "clkin".
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For all output ports, a corresponding, optional child node named OUT1,
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OUT2, etc. can represent a each output, and the node can be used to
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specify the following:
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- idt,mode: can be one of the following:
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- VC5_LVPECL
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- VC5_CMOS
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- VC5_HCSL33
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- VC5_LVDS
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- VC5_CMOS2
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- VC5_CMOSD
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- VC5_HCSL25
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- idt,voltage-microvolts: can be one of the following
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- 1800000
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- 2500000
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- 3300000
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- idt,slew-percent: Percent of normal, can be one of
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- 80
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- 85
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- 90
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- 100
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==Mapping between clock specifier and physical pins==
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When referencing the provided clock in the DT using phandle and
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clock specifier, the following mapping applies:
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5P49V5923:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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5P49V5933:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT4
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5P49V5925 and
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5P49V5935:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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5P49V6901:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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==Example==
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/* 25MHz reference crystal */
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ref25: ref25m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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i2c-master-node {
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/* IDT 5P49V5923 i2c clock generator */
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vc5: clock-generator@6a {
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compatible = "idt,5p49v5923";
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reg = <0x6a>;
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#clock-cells = <1>;
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/* Connect XIN input to 25MHz reference */
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clocks = <&ref25m>;
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clock-names = "xin";
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OUT1 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolts = <1800000>;
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idt,slew-percent = <80>;
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};
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OUT2 {
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...
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};
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...
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};
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};
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/* Consumer referencing the 5P49V5923 pin OUT1 */
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consumer {
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...
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clocks = <&vc5 1>;
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...
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}
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154
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Normal file
154
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Normal file
@ -0,0 +1,154 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
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description: |
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The IDT VersaClock 5 and VersaClock 6 are programmable I2C
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clock generators providing from 3 to 12 output clocks.
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When referencing the provided clock in the DT using phandle and clock
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specifier, the following mapping applies:
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- 5P49V5923:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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- 5P49V5933:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT4
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- other parts:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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maintainers:
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- Luca Ceresoli <luca@lucaceresoli.net>
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properties:
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compatible:
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enum:
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- idt,5p49v5923
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- idt,5p49v5925
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- idt,5p49v5933
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- idt,5p49v5935
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- idt,5p49v6901
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- idt,5p49v6965
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reg:
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description: I2C device address
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enum: [ 0x68, 0x6a ]
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'#clock-cells':
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const: 1
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patternProperties:
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"^OUT[1-4]$":
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type: object
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description:
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Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
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Configuration" in the Versaclock 5/6/6E Family Register Description
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and Programming Guide.
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properties:
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idt,mode:
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description:
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The output drive mode. Values defined in dt-bindings/clk/versaclock.h
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 6
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idt,voltage-microvolt:
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description: The output drive voltage.
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enum: [ 1800000, 2500000, 3300000 ]
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idt,slew-percent:
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description: The Slew rate control for CMOS single-ended.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 80, 85, 90, 100 ]
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required:
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- compatible
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- reg
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- '#clock-cells'
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- idt,5p49v5933
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- idt,5p49v5935
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then:
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# Devices with builtin crystal + optional external input
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properties:
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clock-names:
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const: clkin
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clocks:
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maxItems: 1
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else:
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# Devices without builtin crystal
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properties:
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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enum: [ xin, clkin ]
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clocks:
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minItems: 1
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maxItems: 2
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required:
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- clock-names
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- clocks
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examples:
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- |
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#include <dt-bindings/clk/versaclock.h>
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/* 25MHz reference crystal */
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ref25: ref25m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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i2c@0 {
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reg = <0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* IDT 5P49V5923 I2C clock generator */
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vc5: clock-generator@6a {
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compatible = "idt,5p49v5923";
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reg = <0x6a>;
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#clock-cells = <1>;
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/* Connect XIN input to 25MHz reference */
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clocks = <&ref25m>;
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clock-names = "xin";
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OUT1 {
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idt,drive-mode = <VC5_CMOSD>;
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idt,voltage-microvolts = <1800000>;
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idt,slew-percent = <80>;
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};
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OUT4 {
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idt,drive-mode = <VC5_LVDS>;
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};
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};
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};
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/* Consumer referencing the 5P49V5923 pin OUT1 */
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consumer {
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/* ... */
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clocks = <&vc5 1>;
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/* ... */
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};
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...
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@ -8326,6 +8326,7 @@ F: drivers/input/misc/ideapad_slidebar.c
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IDT VersaClock 5 CLOCK DRIVER
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M: Luca Ceresoli <luca@lucaceresoli.net>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
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F: drivers/clk/clk-versaclock5.c
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IEEE 802.15.4 SUBSYSTEM
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