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ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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@ -25,6 +25,8 @@
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#define SOCFPGA_RSTMGR_MODPERRST 0x14
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#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
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#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
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/* System Manager bits */
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#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
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#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
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@ -54,6 +54,29 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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return 0;
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}
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static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
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if (socfpga_cpu1start_addr) {
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writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
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SOCFPGA_A10_RSTMGR_MODMPURST);
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
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writel(virt_to_phys(socfpga_secondary_startup),
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sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
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flush_cache_all();
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smp_wmb();
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outer_clean_range(0, trampoline_size);
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/* This will release CPU #1 out of reset. */
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writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
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}
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return 0;
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}
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static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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@ -91,4 +114,13 @@ static struct smp_operations socfpga_smp_ops __initdata = {
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#endif
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};
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static struct smp_operations socfpga_a10_smp_ops __initdata = {
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.smp_prepare_cpus = socfpga_smp_prepare_cpus,
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.smp_boot_secondary = socfpga_a10_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = socfpga_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
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CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);
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