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USB: DWC3: Put 100 ms delay for phy to be stable
Before taking core out of reset phy must be stable. So wait for 100ms after clear phy reset. Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -148,6 +148,8 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
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reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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mdelay(100);
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/* After PHYs are stable we can take Core out of reset state */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_CORESOFTRESET;
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