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- Ensure context synchronisation after a write to APIAKey.
- Fix bullet list formatting in Documentation/arm64/amu.rst to eliminate doc warnings. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl6jG6sACgkQa9axLQDI XvFFLQ/+O/AOzG7lMP/7Yoq7+5Tt3kO8CoODHc+q7nE/Kpyn58/Aa1QorzQHM3r9 xZkEWwYZIN/XELHtfD/6m6Z6KmtgPdHN4+UT7kJi6LSy1c4ZN6CUWMBi1RrzEN1O VZx6n8k0EAo6utIa3ncyWlf9+F+ja84756HdZzPtI4DOWnVkZ/A2F6+XiHRSpz+o txjdXVRBLigJiVOHchAV9NU6dhz3O8bnUz2jAoYW0uqIVKz9z53SvN23R+w7Kqsa KRL38OD/gODizc92yi8YpdIpuvQIFywgHXcbFcFf6wgi9pXHiRDDL1Q1URx0op8K 8HjM/PEcbmeBv+QN7JvrtGolqUa2IuU5EcJ/c4hbUlHLU9PoQYHZvGkdbq1aI/Xh x2Jv79qWu4IMyEUQeKxOs3In7TMEwNXc81q6tv3F+1e3w/T6yAl23DNSBhNZQiol +nZ8GUyT4Znov9VXOBXnQsj0KvzIQq7SYTE55VejmDTIiQTZMV13Rj8KEHBr5Cej keUx2Hyv00IHJ7kbg+Luw9DkfCXh4byWIlHb3vPQQUQSbQx4IYroblbohFx/8jAU mEgQSE8E7CnT82GKAWm6lIed8h9erHMr+WUtnXhVhKFaSGCljtWIdog1LbN5vGtV vYs/sXVnmy349NNTOLXCdIOuaUfWCDLOwagPhQwSUPJNwu4h2Q4= =q/zE -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - Ensure context synchronisation after a write to APIAKey. - Fix bullet list formatting in Documentation/arm64/amu.rst to eliminate doc warnings. * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: Documentation: arm64: fix amu.rst doc warnings arm64: sync kernel APIAKey when installing
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4544db3f84
@ -23,13 +23,14 @@ optional external memory-mapped interface.
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Version 1 of the Activity Monitors architecture implements a counter group
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of four fixed and architecturally defined 64-bit event counters.
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- CPU cycle counter: increments at the frequency of the CPU.
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- Constant counter: increments at the fixed frequency of the system
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clock.
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- Instructions retired: increments with every architecturally executed
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instruction.
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- Memory stall cycles: counts instruction dispatch stall cycles caused by
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misses in the last level cache within the clock domain.
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- CPU cycle counter: increments at the frequency of the CPU.
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- Constant counter: increments at the fixed frequency of the system
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clock.
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- Instructions retired: increments with every architecturally executed
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instruction.
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- Memory stall cycles: counts instruction dispatch stall cycles caused by
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misses in the last level cache within the clock domain.
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When in WFI or WFE these counters do not increment.
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@ -57,11 +58,12 @@ counters, only the presence of the extension.
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Firmware (code running at higher exception levels, e.g. arm-tf) support is
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needed to:
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- Enable access for lower exception levels (EL2 and EL1) to the AMU
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registers.
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- Enable the counters. If not enabled these will read as 0.
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- Save/restore the counters before/after the CPU is being put/brought up
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from the 'off' power state.
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- Enable access for lower exception levels (EL2 and EL1) to the AMU
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registers.
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- Enable the counters. If not enabled these will read as 0.
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- Save/restore the counters before/after the CPU is being put/brought up
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from the 'off' power state.
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When using kernels that have this feature enabled but boot with broken
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firmware the user may experience panics or lockups when accessing the
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@ -78,10 +80,11 @@ are not trapped in EL2/EL3.
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The fixed counters of AMUv1 are accessible though the following system
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register definitions:
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- SYS_AMEVCNTR0_CORE_EL0
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- SYS_AMEVCNTR0_CONST_EL0
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- SYS_AMEVCNTR0_INST_RET_EL0
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- SYS_AMEVCNTR0_MEM_STALL_EL0
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- SYS_AMEVCNTR0_CORE_EL0
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- SYS_AMEVCNTR0_CONST_EL0
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- SYS_AMEVCNTR0_INST_RET_EL0
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- SYS_AMEVCNTR0_MEM_STALL_EL0
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Auxiliary platform specific counters can be accessed using
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SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.
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@ -93,9 +96,10 @@ Userspace access
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----------------
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Currently, access from userspace to the AMU registers is disabled due to:
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- Security reasons: they might expose information about code executed in
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secure mode.
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- Purpose: AMU counters are intended for system management use.
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- Security reasons: they might expose information about code executed in
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secure mode.
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- Purpose: AMU counters are intended for system management use.
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Also, the presence of the feature is not visible to userspace.
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@ -105,8 +109,9 @@ Virtualization
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Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
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guest side is disabled due to:
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- Security reasons: they might expose information about code executed
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by other guests or the host.
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- Security reasons: they might expose information about code executed
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by other guests or the host.
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Any attempt to access the AMU registers will result in an UNDEFINED
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exception being injected into the guest.
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@ -47,7 +47,7 @@ static inline void ptrauth_keys_init_user(struct ptrauth_keys_user *keys)
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get_random_bytes(&keys->apga, sizeof(keys->apga));
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}
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#define __ptrauth_key_install(k, v) \
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#define __ptrauth_key_install_nosync(k, v) \
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do { \
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struct ptrauth_key __pki_v = (v); \
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write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \
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@ -62,8 +62,11 @@ static __always_inline void ptrauth_keys_init_kernel(struct ptrauth_keys_kernel
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static __always_inline void ptrauth_keys_switch_kernel(struct ptrauth_keys_kernel *keys)
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{
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if (system_supports_address_auth())
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__ptrauth_key_install(APIA, keys->apia);
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if (!system_supports_address_auth())
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return;
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__ptrauth_key_install_nosync(APIA, keys->apia);
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isb();
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}
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extern int ptrauth_prctl_reset_keys(struct task_struct *tsk, unsigned long arg);
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