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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/amd/display: move dispclk vco freq to clk mgr base
This value will be needed by dml and therefore should be externally accessible. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
e2e316d5d7
commit
44ce0cd3b5
drivers/gpu/drm/amd/display/dc
clk_mgr
dce100
dce112
dcn10
dcn20
dcn21
dcn20
inc/hw
@ -147,7 +147,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
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/* Calculate the current DFS clock, in kHz.*/
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dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->dentist_vco_freq_khz) / target_div;
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* clk_mgr->base.dentist_vco_freq_khz) / target_div;
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return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
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}
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@ -239,7 +239,7 @@ int dce_set_clock(
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->dentist_vco_freq_khz / 64);
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clk_mgr_dce->base.dentist_vco_freq_khz / 64);
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/* Prepare to program display clock*/
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pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
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@ -276,11 +276,11 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
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int i;
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if (bp->integrated_info)
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clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
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clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr_dce->dentist_vco_freq_khz == 0)
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clk_mgr_dce->dentist_vco_freq_khz = 3600000;
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clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
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clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
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clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
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}
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/*update the maximum display clock for each power state*/
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@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->dentist_vco_freq_khz / 62);
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clk_mgr_dce->base.dentist_vco_freq_khz / 62);
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dce_clk_params.target_clock_frequency = requested_clk_khz;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr->dentist_vco_freq_khz / 62);
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clk_mgr->base.dentist_vco_freq_khz / 62);
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dce_clk_params.target_clock_frequency = requested_clk_khz;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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@ -269,11 +269,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
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clk_mgr->base.dprefclk_khz = 600000;
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if (bp->integrated_info)
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clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
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clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr->dentist_vco_freq_khz == 0)
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clk_mgr->dentist_vco_freq_khz = 3600000;
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clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
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if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
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clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr->base.dentist_vco_freq_khz == 0)
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clk_mgr->base.dentist_vco_freq_khz = 3600000;
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}
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if (!debug->disable_dfs_bypass && bp->integrated_info)
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@ -121,9 +121,9 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
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void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
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{
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int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
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* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
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int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
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* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
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uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
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uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
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@ -412,7 +412,7 @@ void dcn20_clk_mgr_construct(
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if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
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dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
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clk_mgr->dentist_vco_freq_khz = 3850000;
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clk_mgr->base.dentist_vco_freq_khz = 3850000;
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} else {
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/* DFS Slice 2 should be used for DPREFCLK */
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@ -436,15 +436,15 @@ void dcn20_clk_mgr_construct(
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pll_req = dc_fixpt_mul_int(pll_req, 100000);
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/* integer part is now VCO frequency in kHz */
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clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
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clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
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/* in case we don't get a value from the register, use default */
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if (clk_mgr->dentist_vco_freq_khz == 0)
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clk_mgr->dentist_vco_freq_khz = 3850000;
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if (clk_mgr->base.dentist_vco_freq_khz == 0)
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clk_mgr->base.dentist_vco_freq_khz = 3850000;
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/* Calculate the DPREFCLK in kHz.*/
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clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr->dentist_vco_freq_khz) / target_div;
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* clk_mgr->base.dentist_vco_freq_khz) / target_div;
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}
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//Integrated_info table does not exist on dGPU projects so should not be referenced
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//anywhere in code for dGPUs.
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@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
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}
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};
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void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
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static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
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{
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int i, num_valid_sets;
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@ -542,7 +542,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
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return 0;
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}
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void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
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static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
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{
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int i, j = 0;
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@ -628,17 +628,17 @@ void rn_clk_mgr_construct(
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if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
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dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
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clk_mgr->dentist_vco_freq_khz = 3600000;
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clk_mgr->base.dentist_vco_freq_khz = 3600000;
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clk_mgr->base.dprefclk_khz = 600000;
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} else {
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struct clk_log_info log_info = {0};
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/* TODO: Check we get what we expect during bringup */
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clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
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clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
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/* in case we don't get a value from the register, use default */
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if (clk_mgr->dentist_vco_freq_khz == 0)
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clk_mgr->dentist_vco_freq_khz = 3600000;
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if (clk_mgr->base.dentist_vco_freq_khz == 0)
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clk_mgr->base.dentist_vco_freq_khz = 3600000;
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rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
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/* Convert dprefclk units from MHz to KHz */
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@ -33,13 +33,6 @@ struct rn_clk_registers {
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uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
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};
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void rn_build_watermark_ranges(
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struct clk_bw_params *bw_params,
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struct pp_smu_wm_range_sets *ranges);
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void rn_clk_mgr_helper_populate_bw_params(
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struct clk_bw_params *bw_params,
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struct dpm_clocks *clock_table,
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struct hw_asic_id *asic_id);
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void rn_clk_mgr_construct(struct dc_context *ctx,
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struct clk_mgr_internal *clk_mgr,
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struct pp_smu_funcs *pp_smu,
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@ -3002,7 +3002,7 @@ static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
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}
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}
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static void cap_soc_clocks(
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void dcn20_cap_soc_clocks(
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struct _vcs_dpi_soc_bounding_box_st *bb,
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struct pp_smu_nv_clock_table max_clocks)
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{
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@ -3069,7 +3069,7 @@ static void cap_soc_clocks(
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}
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}
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static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
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void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
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struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
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{
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struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
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@ -3127,7 +3127,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
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bb->clock_limits[num_calculated_states].state = bb->num_states;
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}
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static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
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void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
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{
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kernel_fpu_begin();
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if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
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@ -3326,14 +3326,14 @@ static bool init_soc_bounding_box(struct dc *dc,
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}
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if (clock_limits_available && uclk_states_available && num_states)
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update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
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dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
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else if (clock_limits_available)
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cap_soc_clocks(loaded_bb, max_clocks);
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dcn20_cap_soc_clocks(loaded_bb, max_clocks);
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}
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loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
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loaded_ip->max_num_dpp = pool->base.pipe_count;
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patch_bounding_box(dc, loaded_bb);
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dcn20_patch_bounding_box(dc, loaded_bb);
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return true;
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}
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@ -95,6 +95,12 @@ struct display_stream_compressor *dcn20_dsc_create(
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struct dc_context *ctx, uint32_t inst);
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void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
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void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
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void dcn20_cap_soc_clocks(
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struct _vcs_dpi_soc_bounding_box_st *bb,
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struct pp_smu_nv_clock_table max_clocks);
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void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
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struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
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struct hubp *dcn20_hubp_create(
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struct dc_context *ctx,
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uint32_t inst);
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@ -149,7 +149,6 @@ struct wm_table {
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struct clk_bw_params {
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unsigned int vram_type;
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unsigned int num_channels;
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unsigned int dispclk_vco_khz;
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struct clk_limit_table clk_table;
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struct wm_table wm_table;
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};
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@ -192,6 +191,7 @@ struct clk_mgr {
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struct dc_clocks clks;
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bool psr_allow_active_cache;
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int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
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int dentist_vco_freq_khz;
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#ifdef CONFIG_DRM_AMD_DC_DCN2_1
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struct clk_bw_params *bw_params;
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#endif
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@ -225,8 +225,6 @@ struct clk_mgr_internal {
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struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
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/*TODO: figure out which of the below fields should be here vs in asic specific portion */
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int dentist_vco_freq_khz;
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/* Cache the status of DFS-bypass feature*/
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bool dfs_bypass_enabled;
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/* True if the DFS-bypass feature is enabled and active. */
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