diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 62a6735ada9e..5240153c15ba 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -551,6 +551,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
 
 	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
 	val &= ~PORT_LINK_FAST_LINK_MODE;
+	val |= PORT_LINK_DLL_LINK_EN;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
 	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 2c0d32ffb828..d15e49b8df2a 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -164,10 +164,6 @@ static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp)
 	val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) |
 	       FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts);
 	pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val);
-
-	/* Port Link Control Register */
-	pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_LINK_CONTROL, PORT_LINK_DLL_LINK_EN,
-			    PORT_LINK_DLL_LINK_EN);
 }
 
 static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)