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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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regulator: Add support for twl6030 regulators
This patch updates the regulator driver to add support for TWL6030 PMIC specific LDO regulators. SMPS resources are not yet supported for TWL6030 and also .set_mode and .get_status for LDO's are yet to be implemented for TWL6030. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Rajendra Nayak
Samuel Ortiz
parent
a6b49ffd2d
commit
441a450554
@ -70,7 +70,7 @@ config REGULATOR_MAX1586
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for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
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config REGULATOR_TWL4030
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bool "TI TWL4030/TWL5030/TPS695x0 PMIC"
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bool "TI TWL4030/TWL5030/TWL6030/TPS695x0 PMIC"
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depends on TWL4030_CORE
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help
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This driver supports the voltage regulators provided by
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@ -52,27 +52,38 @@ struct twlreg_info {
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* The first three registers of all power resource banks help hardware to
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* manage the various resource groups.
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*/
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/* Common offset in TWL4030/6030 */
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#define VREG_GRP 0
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/* TWL4030 register offsets */
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#define VREG_TYPE 1
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#define VREG_REMAP 2
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#define VREG_DEDICATED 3 /* LDO control */
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/* TWL6030 register offsets */
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#define VREG_TRANS 1
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#define VREG_STATE 2
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#define VREG_VOLTAGE 3
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/* TWL6030 Misc register offsets */
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#define VREG_BC_ALL 1
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#define VREG_BC_REF 2
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#define VREG_BC_PROC 3
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#define VREG_BC_CLK_RST 4
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static inline int
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twlreg_read(struct twlreg_info *info, unsigned offset)
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twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
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{
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u8 value;
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int status;
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status = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER,
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status = twl_i2c_read_u8(slave_subgp,
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&value, info->base + offset);
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return (status < 0) ? status : value;
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}
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static inline int
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twlreg_write(struct twlreg_info *info, unsigned offset, u8 value)
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twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
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u8 value)
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{
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return twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
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return twl_i2c_write_u8(slave_subgp,
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value, info->base + offset);
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}
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@ -82,17 +93,22 @@ twlreg_write(struct twlreg_info *info, unsigned offset, u8 value)
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static int twlreg_grp(struct regulator_dev *rdev)
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{
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return twlreg_read(rdev_get_drvdata(rdev), VREG_GRP);
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return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
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VREG_GRP);
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}
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/*
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* Enable/disable regulators by joining/leaving the P1 (processor) group.
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* We assume nobody else is updating the DEV_GRP registers.
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*/
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#define P3_GRP BIT(7) /* "peripherals" */
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#define P2_GRP BIT(6) /* secondary processor, modem, etc */
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#define P1_GRP BIT(5) /* CPU/Linux */
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/* definition for 4030 family */
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#define P3_GRP_4030 BIT(7) /* "peripherals" */
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#define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */
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#define P1_GRP_4030 BIT(5) /* CPU/Linux */
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/* definition for 6030 family */
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#define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
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#define P2_GRP_6030 BIT(1) /* "peripherals" */
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#define P1_GRP_6030 BIT(0) /* CPU/Linux */
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static int twlreg_is_enabled(struct regulator_dev *rdev)
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{
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@ -101,7 +117,11 @@ static int twlreg_is_enabled(struct regulator_dev *rdev)
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if (state < 0)
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return state;
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return (state & P1_GRP) != 0;
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if (twl_class_is_4030())
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state &= P1_GRP_4030;
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else
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state &= P1_GRP_6030;
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return state;
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}
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static int twlreg_enable(struct regulator_dev *rdev)
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@ -109,12 +129,16 @@ static int twlreg_enable(struct regulator_dev *rdev)
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struct twlreg_info *info = rdev_get_drvdata(rdev);
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int grp;
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grp = twlreg_read(info, VREG_GRP);
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grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP);
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if (grp < 0)
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return grp;
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grp |= P1_GRP;
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return twlreg_write(info, VREG_GRP, grp);
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if (twl_class_is_4030())
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grp |= P1_GRP_4030;
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else
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grp |= P1_GRP_6030;
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return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
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}
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static int twlreg_disable(struct regulator_dev *rdev)
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@ -122,18 +146,25 @@ static int twlreg_disable(struct regulator_dev *rdev)
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struct twlreg_info *info = rdev_get_drvdata(rdev);
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int grp;
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grp = twlreg_read(info, VREG_GRP);
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grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP);
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if (grp < 0)
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return grp;
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grp &= ~P1_GRP;
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return twlreg_write(info, VREG_GRP, grp);
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if (twl_class_is_4030())
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grp &= ~P1_GRP_4030;
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else
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grp &= ~P1_GRP_6030;
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return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
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}
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static int twlreg_get_status(struct regulator_dev *rdev)
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{
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int state = twlreg_grp(rdev);
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if (twl_class_is_6030())
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return 0; /* FIXME return for 6030 regulator */
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if (state < 0)
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return state;
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state &= 0x0f;
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@ -152,6 +183,9 @@ static int twlreg_set_mode(struct regulator_dev *rdev, unsigned mode)
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unsigned message;
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int status;
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if (twl_class_is_6030())
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return 0; /* FIXME return for 6030 regulator */
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/* We can only set the mode through state machine commands... */
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switch (mode) {
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case REGULATOR_MODE_NORMAL:
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@ -168,7 +202,7 @@ static int twlreg_set_mode(struct regulator_dev *rdev, unsigned mode)
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status = twlreg_grp(rdev);
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if (status < 0)
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return status;
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if (!(status & (P3_GRP | P2_GRP | P1_GRP)))
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if (!(status & (P3_GRP_4030 | P2_GRP_4030 | P1_GRP_4030)))
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return -EACCES;
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status = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
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@ -260,7 +294,29 @@ static const u16 VSIM_VSEL_table[] = {
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static const u16 VDAC_VSEL_table[] = {
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1200, 1300, 1800, 1800,
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};
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static const u16 VAUX1_6030_VSEL_table[] = {
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1000, 1300, 1800, 2500,
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2800, 2900, 3000, 3000,
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};
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static const u16 VAUX2_6030_VSEL_table[] = {
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1200, 1800, 2500, 2750,
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2800, 2800, 2800, 2800,
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};
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static const u16 VAUX3_6030_VSEL_table[] = {
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1000, 1200, 1300, 1800,
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2500, 2800, 3000, 3000,
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};
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static const u16 VMMC_VSEL_table[] = {
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1200, 1800, 2800, 2900,
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3000, 3000, 3000, 3000,
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};
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static const u16 VPP_VSEL_table[] = {
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1800, 1900, 2000, 2100,
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2200, 2300, 2400, 2500,
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};
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static const u16 VUSIM_VSEL_table[] = {
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1200, 1800, 2500, 2900,
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};
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static int twlldo_list_voltage(struct regulator_dev *rdev, unsigned index)
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{
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@ -288,7 +344,8 @@ twlldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV)
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/* use the first in-range value */
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if (min_uV <= uV && uV <= max_uV)
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return twlreg_write(info, VREG_DEDICATED, vsel);
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return twlreg_write(info, TWL_MODULE_PM_RECEIVER,
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VREG_VOLTAGE, vsel);
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}
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return -EDOM;
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@ -297,7 +354,8 @@ twlldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV)
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static int twlldo_get_voltage(struct regulator_dev *rdev)
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{
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struct twlreg_info *info = rdev_get_drvdata(rdev);
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int vsel = twlreg_read(info, VREG_DEDICATED);
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int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER,
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VREG_VOLTAGE);
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if (vsel < 0)
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return vsel;
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@ -360,6 +418,10 @@ static struct regulator_ops twlfixed_ops = {
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TWL_ADJUSTABLE_LDO(label, offset, num, TWL4030)
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#define TWL4030_FIXED_LDO(label, offset, mVolts, num) \
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TWL_FIXED_LDO(label, offset, mVolts, num, TWL4030)
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#define TWL6030_ADJUSTABLE_LDO(label, offset, num) \
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TWL_ADJUSTABLE_LDO(label, offset, num, TWL6030)
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#define TWL6030_FIXED_LDO(label, offset, mVolts, num) \
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TWL_FIXED_LDO(label, offset, mVolts, num, TWL6030)
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#define TWL_ADJUSTABLE_LDO(label, offset, num, family) { \
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.base = offset, \
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@ -420,6 +482,18 @@ static struct twlreg_info twl_regs[] = {
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TWL4030_FIXED_LDO(VUSB1V8, 0x74, 1800, 18),
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TWL4030_FIXED_LDO(VUSB3V1, 0x77, 3100, 19),
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/* VUSBCP is managed *only* by the USB subchip */
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/* 6030 REG with base as PMC Slave Misc : 0x0030 */
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TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1),
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TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 2),
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TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 3),
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TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 4),
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TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 5),
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TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 7),
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TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15),
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TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16),
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TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17),
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TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18)
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};
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static int twlreg_probe(struct platform_device *pdev)
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@ -427,6 +427,12 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
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#define MSG_SINGULAR(devgrp, id, state) \
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((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
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#define MSG_BROADCAST_ALL(devgrp, state) \
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((devgrp) << 5 | (state))
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#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
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#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
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#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
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/*----------------------------------------------------------------------*/
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struct twl4030_clock_init_data {
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@ -602,6 +608,7 @@ int twl4030_sih_setup(int module);
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* VIO is generally fixed.
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*/
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/* TWL4030 SMPS/LDO's */
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/* EXTERNAL dc-to-dc buck converters */
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#define TWL4030_REG_VDD1 0
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#define TWL4030_REG_VDD2 1
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@ -628,4 +635,31 @@ int twl4030_sih_setup(int module);
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#define TWL4030_REG_VUSB1V8 18
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#define TWL4030_REG_VUSB3V1 19
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/* TWL6030 SMPS/LDO's */
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/* EXTERNAL dc-to-dc buck convertor contollable via SR */
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#define TWL6030_REG_VDD1 30
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#define TWL6030_REG_VDD2 31
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#define TWL6030_REG_VDD3 32
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/* Non SR compliant dc-to-dc buck convertors */
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#define TWL6030_REG_VMEM 33
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#define TWL6030_REG_V2V1 34
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#define TWL6030_REG_V1V29 35
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#define TWL6030_REG_V1V8 36
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/* EXTERNAL LDOs */
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#define TWL6030_REG_VAUX1_6030 37
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#define TWL6030_REG_VAUX2_6030 38
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#define TWL6030_REG_VAUX3_6030 39
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#define TWL6030_REG_VMMC 40
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#define TWL6030_REG_VPP 41
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#define TWL6030_REG_VUSIM 42
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#define TWL6030_REG_VANA 43
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#define TWL6030_REG_VCXIO 44
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#define TWL6030_REG_VDAC 45
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#define TWL6030_REG_VUSB 46
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/* INTERNAL LDOs */
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#define TWL6030_REG_VRTC 47
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#endif /* End of __TWL4030_H */
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