mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 18:36:39 +07:00
x86/uv: Use hierarchical irqdomain to manage UV interrupts
Enhance UV code to support hierarchical irqdomain, it helps to make the architecture more clear. We construct hwirq based on mmr_blade and mmr_offset, but mmr_offset has type unsigned long, it may exceed the range of irq_hw_number_t. So help about the way to construct hwirq based on mmr_blade and mmr_offset is welcomed! Folded a patch from Dimitri Sivanich <sivanich@sgi.com> to fix a bug on UV platforms, please refer to: http://lkml.org/lkml/2014/12/16/351 Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Russ Anderson <rja@sgi.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Link: http://lkml.kernel.org/r/1428905519-23704-23-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
parent
49e07d8f28
commit
43fe1abc18
@ -123,6 +123,7 @@ enum irq_alloc_type {
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X86_IRQ_ALLOC_TYPE_MSI,
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X86_IRQ_ALLOC_TYPE_MSIX,
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X86_IRQ_ALLOC_TYPE_DMAR,
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X86_IRQ_ALLOC_TYPE_UV,
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};
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struct irq_alloc_info {
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@ -168,6 +169,14 @@ struct irq_alloc_info {
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struct pci_dev *ht_dev;
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void *ht_update;
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};
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#endif
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#ifdef CONFIG_X86_UV
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struct {
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int uv_limit;
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int uv_blade;
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unsigned long uv_offset;
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char *uv_name;
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};
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#endif
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};
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};
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@ -19,133 +19,18 @@
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#include <asm/uv/uv_hub.h>
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/* MMR offset and pnode of hub sourcing interrupts for a given irq */
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struct uv_irq_2_mmr_pnode{
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struct rb_node list;
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struct uv_irq_2_mmr_pnode {
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unsigned long offset;
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int pnode;
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int irq;
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};
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static DEFINE_SPINLOCK(uv_irq_lock);
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static struct rb_root uv_irq_root;
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static int uv_set_irq_affinity(struct irq_data *, const struct cpumask *, bool);
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static void uv_noop(struct irq_data *data) { }
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static void uv_ack_apic(struct irq_data *data)
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static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
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{
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ack_APIC_irq();
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}
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static struct irq_chip uv_irq_chip = {
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.name = "UV-CORE",
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.irq_mask = uv_noop,
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.irq_unmask = uv_noop,
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.irq_eoi = uv_ack_apic,
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.irq_set_affinity = uv_set_irq_affinity,
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};
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/*
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* Add offset and pnode information of the hub sourcing interrupts to the
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* rb tree for a specific irq.
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*/
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static int uv_set_irq_2_mmr_info(int irq, unsigned long offset, unsigned blade)
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{
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struct rb_node **link = &uv_irq_root.rb_node;
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struct rb_node *parent = NULL;
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struct uv_irq_2_mmr_pnode *n;
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struct uv_irq_2_mmr_pnode *e;
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unsigned long irqflags;
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n = kmalloc_node(sizeof(struct uv_irq_2_mmr_pnode), GFP_KERNEL,
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uv_blade_to_memory_nid(blade));
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if (!n)
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return -ENOMEM;
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n->irq = irq;
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n->offset = offset;
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n->pnode = uv_blade_to_pnode(blade);
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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/* Find the right place in the rbtree: */
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while (*link) {
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parent = *link;
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e = rb_entry(parent, struct uv_irq_2_mmr_pnode, list);
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if (unlikely(irq == e->irq)) {
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/* irq entry exists */
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e->pnode = uv_blade_to_pnode(blade);
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e->offset = offset;
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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kfree(n);
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return 0;
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}
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if (irq < e->irq)
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link = &(*link)->rb_left;
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else
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link = &(*link)->rb_right;
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}
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/* Insert the node into the rbtree. */
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rb_link_node(&n->list, parent, link);
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rb_insert_color(&n->list, &uv_irq_root);
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return 0;
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}
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/* Retrieve offset and pnode information from the rb tree for a specific irq */
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int uv_irq_2_mmr_info(int irq, unsigned long *offset, int *pnode)
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{
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struct uv_irq_2_mmr_pnode *e;
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struct rb_node *n;
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unsigned long irqflags;
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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n = uv_irq_root.rb_node;
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while (n) {
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e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
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if (e->irq == irq) {
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*offset = e->offset;
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*pnode = e->pnode;
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return 0;
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}
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if (irq < e->irq)
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n = n->rb_left;
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else
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n = n->rb_right;
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}
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return -1;
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}
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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static int
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arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
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unsigned long mmr_offset, int limit)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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int mmr_pnode;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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if (limit == UV_AFFINITY_CPU)
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irq_set_status_flags(irq, IRQ_NO_BALANCING);
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else
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irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
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irq_set_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
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irq_name);
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sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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@ -157,68 +42,135 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
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entry->mask = 0;
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entry->dest = cfg->dest_apicid;
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mmr_pnode = uv_blade_to_pnode(mmr_blade);
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return irq;
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uv_write_global_mmr64(info->pnode, info->offset, mmr_value);
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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static void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
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static void uv_noop(struct irq_data *data) { }
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static void uv_ack_apic(struct irq_data *data)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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ack_APIC_irq();
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}
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static int
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uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_data *parent = data->parent_data;
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struct irq_cfg *cfg = irqd_cfg(data);
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unsigned int dest;
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unsigned long mmr_value, mmr_offset;
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struct uv_IO_APIC_route_entry *entry;
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int mmr_pnode;
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int ret;
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if (apic_set_affinity(data, mask, &dest))
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return -1;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret >= 0) {
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uv_program_mmr(cfg, data->chip_data);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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}
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return ret;
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}
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static struct irq_chip uv_irq_chip = {
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.name = "UV-CORE",
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.irq_mask = uv_noop,
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.irq_unmask = uv_noop,
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.irq_eoi = uv_ack_apic,
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.irq_set_affinity = uv_set_irq_affinity,
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};
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static int uv_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct uv_irq_2_mmr_pnode *chip_data;
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struct irq_alloc_info *info = arg;
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struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
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int ret;
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if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_UV)
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return -EINVAL;
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chip_data = kmalloc_node(sizeof(*chip_data), GFP_KERNEL,
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irq_data->node);
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if (!chip_data)
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return -ENOMEM;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret >= 0) {
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if (info->uv_limit == UV_AFFINITY_CPU)
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irq_set_status_flags(virq, IRQ_NO_BALANCING);
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else
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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chip_data->pnode = uv_blade_to_pnode(info->uv_blade);
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chip_data->offset = info->uv_offset;
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irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data,
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handle_percpu_irq, NULL, info->uv_name);
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} else {
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kfree(chip_data);
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}
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return ret;
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}
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static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
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BUG_ON(nr_irqs != 1);
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kfree(irq_data->chip_data);
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irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
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irq_clear_status_flags(virq, IRQ_NO_BALANCING);
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irq_domain_free_irqs_top(domain, virq, nr_irqs);
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}
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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static void uv_domain_activate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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static void uv_domain_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
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}
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = dest;
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static struct irq_domain_ops uv_domain_ops = {
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.alloc = uv_domain_alloc,
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.free = uv_domain_free,
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.activate = uv_domain_activate,
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.deactivate = uv_domain_deactivate,
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};
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/* Get previously stored MMR and pnode of hub sourcing interrupts */
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if (uv_irq_2_mmr_info(data->irq, &mmr_offset, &mmr_pnode))
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return -1;
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static struct irq_domain *uv_get_irq_domain(void)
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{
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static struct irq_domain *uv_domain;
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static DEFINE_MUTEX(uv_lock);
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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mutex_lock(&uv_lock);
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if (uv_domain == NULL) {
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uv_domain = irq_domain_add_tree(NULL, &uv_domain_ops, NULL);
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if (uv_domain)
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uv_domain->parent = x86_vector_domain;
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}
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mutex_unlock(&uv_lock);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return IRQ_SET_MASK_OK_NOCOPY;
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return uv_domain;
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}
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/*
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@ -229,23 +181,21 @@ uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
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int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
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unsigned long mmr_offset, int limit)
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{
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int ret, irq;
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struct irq_alloc_info info;
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struct irq_domain *domain = uv_get_irq_domain();
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if (!domain)
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return -ENOMEM;
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init_irq_alloc_info(&info, cpumask_of(cpu));
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irq = irq_domain_alloc_irqs(NULL, 1, uv_blade_to_memory_nid(mmr_blade),
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&info);
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if (irq <= 0)
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return -EBUSY;
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info.type = X86_IRQ_ALLOC_TYPE_UV;
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info.uv_limit = limit;
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info.uv_blade = mmr_blade;
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info.uv_offset = mmr_offset;
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info.uv_name = irq_name;
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ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
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limit);
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if (ret == irq)
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uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
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else
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irq_domain_free_irqs(irq, 1);
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return ret;
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return irq_domain_alloc_irqs(domain, 1,
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uv_blade_to_memory_nid(mmr_blade), &info);
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}
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EXPORT_SYMBOL_GPL(uv_setup_irq);
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@ -258,26 +208,6 @@ EXPORT_SYMBOL_GPL(uv_setup_irq);
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*/
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void uv_teardown_irq(unsigned int irq)
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{
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struct uv_irq_2_mmr_pnode *e;
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struct rb_node *n;
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unsigned long irqflags;
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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n = uv_irq_root.rb_node;
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while (n) {
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e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
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if (e->irq == irq) {
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arch_disable_uv_irq(e->pnode, e->offset);
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rb_erase(n, &uv_irq_root);
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kfree(e);
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break;
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}
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if (irq < e->irq)
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n = n->rb_left;
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else
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n = n->rb_right;
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}
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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irq_domain_free_irqs(irq, 1);
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}
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EXPORT_SYMBOL_GPL(uv_teardown_irq);
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