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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 19:07:32 +07:00
drm/radeon: expose render backend mask to the userspace
This will allow userspace to correctly program the PA_SC_RASTER_CONFIG register, so it can be considered a fix. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -3114,6 +3114,8 @@ static void cik_setup_rb(struct radeon_device *rdev,
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mask <<= 1;
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}
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rdev->config.cik.backend_enable_mask = enabled_rbs;
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for (i = 0; i < se_num; i++) {
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cik_select_se_sh(rdev, i, 0xffffffff);
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data = 0;
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@ -1940,7 +1940,7 @@ struct si_asic {
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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unsigned num_backends_per_se;
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unsigned backend_enable_mask;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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@ -1970,7 +1970,7 @@ struct cik_asic {
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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unsigned num_backends_per_se;
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unsigned backend_enable_mask;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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@ -461,6 +461,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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case RADEON_INFO_SI_CP_DMA_COMPUTE:
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*value = 1;
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break;
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case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
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if (rdev->family >= CHIP_BONAIRE) {
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*value = rdev->config.cik.backend_enable_mask;
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} else if (rdev->family >= CHIP_TAHITI) {
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*value = rdev->config.si.backend_enable_mask;
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} else {
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DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
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}
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break;
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->request);
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return -EINVAL;
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@ -2855,6 +2855,8 @@ static void si_setup_rb(struct radeon_device *rdev,
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mask <<= 1;
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}
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rdev->config.si.backend_enable_mask = enabled_rbs;
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for (i = 0; i < se_num; i++) {
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si_select_se_sh(rdev, i, 0xffffffff);
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data = 0;
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@ -983,6 +983,8 @@ struct drm_radeon_cs {
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#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
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/* CIK macrotile mode array */
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#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
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/* query the number of render backends */
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#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
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struct drm_radeon_info {
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