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bnx2x: Add Idlechk related register definitions.
The patch adds register definitions required for Idlechk implementation. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -7639,6 +7639,82 @@ Theotherbitsarereservedandshouldbezero*/
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(0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
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#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
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/* IdleChk registers */
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#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc
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#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8
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#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0
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#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc
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#define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778
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#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c
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#define PXP2_REG_RQ_GARB 0x120748
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc
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#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0
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#define PBF_REG_CREDIT_Q2 0x140344
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#define PBF_REG_CREDIT_Q3 0x140348
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#define PBF_REG_CREDIT_Q4 0x14034c
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#define PBF_REG_CREDIT_Q5 0x140350
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#define PBF_REG_INIT_CRD_Q2 0x15c238
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#define PBF_REG_INIT_CRD_Q3 0x15c23c
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#define PBF_REG_INIT_CRD_Q4 0x15c240
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#define PBF_REG_INIT_CRD_Q5 0x15c244
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#define PBF_REG_TASK_CNT_Q0 0x140374
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#define PBF_REG_TASK_CNT_Q1 0x140378
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#define PBF_REG_TASK_CNT_Q2 0x14037c
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#define PBF_REG_TASK_CNT_Q3 0x140380
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#define PBF_REG_TASK_CNT_Q4 0x140384
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#define PBF_REG_TASK_CNT_Q5 0x140388
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#define PBF_REG_TASK_CNT_LB_Q 0x140370
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#define QM_REG_BYTECRD0 0x16e6fc
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#define QM_REG_BYTECRD1 0x16e700
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#define QM_REG_BYTECRD2 0x16e704
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#define QM_REG_BYTECRD3 0x16e7ac
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#define QM_REG_BYTECRD4 0x16e7b0
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#define QM_REG_BYTECRD5 0x16e7b4
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#define QM_REG_BYTECRD6 0x16e7b8
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#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
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#define QM_REG_BYTECRDERRREG 0x16e708
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#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714
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#define QM_REG_VOQCREDIT_2 0x1682d8
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#define QM_REG_VOQCREDIT_3 0x1682dc
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#define QM_REG_VOQCREDIT_5 0x1682e4
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#define QM_REG_VOQCREDIT_6 0x1682e8
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#define QM_REG_VOQINITCREDIT_3 0x16806c
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#define QM_REG_VOQINITCREDIT_6 0x168078
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#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc
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#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0
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#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4
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#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8
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#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc
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#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0
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#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4
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#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8
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#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec
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#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8
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#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530
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#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538
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#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508
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#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460
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#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474
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#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418
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#define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420
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#define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428
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#define NIG_REG_LLH0_FIFO_EMPTY 0x10548
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#define NIG_REG_LLH1_FIFO_EMPTY 0x10558
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#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8
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#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308
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#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318
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#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348
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#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570
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#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578
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#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c
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#define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630
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#define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634
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#define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638
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/******************************************************************************
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* Description:
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* Calculates crc 8 on a word value: polynomial 0-1-2-8
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@ -7697,6 +7773,4 @@ static inline u8 calc_crc8(u32 data, u8 crc)
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return crc_res;
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}
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#endif /* BNX2X_REG_H */
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