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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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qed: Populate nvm image attribute shadow.
This patch adds support for populating the flash image attributes. Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com> Signed-off-by: Ariel Elior <ariel.elior@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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50bc60cb15
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43645ce03e
@ -437,6 +437,11 @@ enum BAR_ID {
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BAR_ID_1 /* Used for doorbells */
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};
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struct qed_nvm_image_info {
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u32 num_images;
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struct bist_nvm_image_att *image_att;
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};
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#define DRV_MODULE_VERSION \
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__stringify(QED_MAJOR_VERSION) "." \
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__stringify(QED_MINOR_VERSION) "." \
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@ -561,6 +566,9 @@ struct qed_hwfn {
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/* L2-related */
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struct qed_l2_info *p_l2_info;
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/* Nvm images number and attributes */
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struct qed_nvm_image_info nvm_info;
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struct qed_ptt *p_arfs_ptt;
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struct qed_simd_fp_handler simd_proto_handler[64];
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@ -2932,6 +2932,12 @@ static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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return 0;
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}
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static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
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{
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kfree(p_hwfn->nvm_info.image_att);
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p_hwfn->nvm_info.image_att = NULL;
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}
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static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
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void __iomem *p_regview,
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void __iomem *p_doorbells,
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@ -2995,12 +3001,25 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
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DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
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}
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/* NVRAM info initialization and population */
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if (IS_LEAD_HWFN(p_hwfn)) {
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rc = qed_mcp_nvm_info_populate(p_hwfn);
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if (rc) {
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DP_NOTICE(p_hwfn,
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"Failed to populate nvm info shadow\n");
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goto err2;
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}
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}
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/* Allocate the init RT array and initialize the init-ops engine */
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rc = qed_init_alloc(p_hwfn);
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if (rc)
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goto err2;
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goto err3;
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return rc;
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err3:
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if (IS_LEAD_HWFN(p_hwfn))
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qed_nvm_info_free(p_hwfn);
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err2:
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if (IS_LEAD_HWFN(p_hwfn))
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qed_iov_free_hw_info(p_hwfn->cdev);
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@ -3056,6 +3075,7 @@ int qed_hw_prepare(struct qed_dev *cdev,
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if (rc) {
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if (IS_PF(cdev)) {
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qed_init_free(p_hwfn);
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qed_nvm_info_free(p_hwfn);
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qed_mcp_free(p_hwfn);
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qed_hw_hwfn_free(p_hwfn);
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}
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@ -3088,6 +3108,8 @@ void qed_hw_remove(struct qed_dev *cdev)
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}
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qed_iov_free_hw_info(cdev);
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qed_nvm_info_free(p_hwfn);
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}
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static void qed_chain_free_next_ptr(struct qed_dev *cdev,
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@ -2303,9 +2303,9 @@ int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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return rc;
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}
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int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 *num_images)
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int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 *num_images)
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{
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u32 drv_mb_param = 0, rsp;
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int rc = 0;
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@ -2324,10 +2324,10 @@ int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
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return rc;
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}
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int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct bist_nvm_image_att *p_image_att,
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u32 image_index)
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int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct bist_nvm_image_att *p_image_att,
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u32 image_index)
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{
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u32 buf_size = 0, param, resp = 0, resp_param = 0;
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int rc;
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@ -2351,16 +2351,71 @@ int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
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return rc;
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}
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int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
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{
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struct qed_nvm_image_info *nvm_info = &p_hwfn->nvm_info;
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struct qed_ptt *p_ptt;
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int rc;
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u32 i;
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt) {
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DP_ERR(p_hwfn, "failed to acquire ptt\n");
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return -EBUSY;
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}
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/* Acquire from MFW the amount of available images */
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nvm_info->num_images = 0;
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rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
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p_ptt, &nvm_info->num_images);
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if (rc == -EOPNOTSUPP) {
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DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
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goto out;
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} else if (rc || !nvm_info->num_images) {
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DP_ERR(p_hwfn, "Failed getting number of images\n");
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goto err0;
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}
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nvm_info->image_att = kmalloc(nvm_info->num_images *
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sizeof(struct bist_nvm_image_att),
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GFP_KERNEL);
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if (!nvm_info->image_att) {
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rc = -ENOMEM;
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goto err0;
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}
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/* Iterate over images and get their attributes */
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for (i = 0; i < nvm_info->num_images; i++) {
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rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
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&nvm_info->image_att[i], i);
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if (rc) {
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DP_ERR(p_hwfn,
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"Failed getting image index %d attributes\n", i);
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goto err1;
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}
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DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
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nvm_info->image_att[i].len);
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}
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out:
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qed_ptt_release(p_hwfn, p_ptt);
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return 0;
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err1:
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kfree(nvm_info->image_att);
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err0:
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qed_ptt_release(p_hwfn, p_ptt);
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return rc;
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}
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static int
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qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_nvm_images image_id,
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struct qed_nvm_image_att *p_image_att)
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{
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struct bist_nvm_image_att mfw_image_att;
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enum nvm_image_type type;
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u32 num_images, i;
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int rc;
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u32 i;
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/* Translate image_id into MFW definitions */
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switch (image_id) {
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@ -2376,29 +2431,18 @@ qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
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return -EINVAL;
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}
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/* Learn number of images, then traverse and see if one fits */
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rc = qed_mcp_bist_nvm_test_get_num_images(p_hwfn, p_ptt, &num_images);
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if (rc || !num_images)
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return -EINVAL;
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for (i = 0; i < num_images; i++) {
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rc = qed_mcp_bist_nvm_test_get_image_att(p_hwfn, p_ptt,
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&mfw_image_att, i);
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if (rc)
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return rc;
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if (type == mfw_image_att.image_type)
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for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
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if (type == p_hwfn->nvm_info.image_att[i].image_type)
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break;
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}
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if (i == num_images) {
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if (i == p_hwfn->nvm_info.num_images) {
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DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
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"Failed to find nvram image of type %08x\n",
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image_id);
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return -EINVAL;
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return -ENOENT;
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}
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p_image_att->start_addr = mfw_image_att.nvm_start_addr;
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p_image_att->length = mfw_image_att.len;
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p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
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p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
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return 0;
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}
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@ -496,9 +496,9 @@ int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn,
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 *num_images);
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int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 *num_images);
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/**
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* @brief Bist nvm test - get image attributes by index
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@ -510,10 +510,10 @@ int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct bist_nvm_image_att *p_image_att,
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u32 image_index);
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int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct bist_nvm_image_att *p_image_att,
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u32 image_index);
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/* Using hwfn number (and not pf_num) is required since in CMT mode,
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* same pf_num may be used by two different hwfn
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@ -957,4 +957,12 @@ int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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* @param p_ptt
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*/
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int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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/**
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* @brief Populate the nvm info shadow in the given hardware function
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*
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* @param p_hwfn
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*/
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int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn);
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#endif
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@ -125,7 +125,7 @@ int qed_selftest_nvram(struct qed_dev *cdev)
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}
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/* Acquire from MFW the amount of available images */
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rc = qed_mcp_bist_nvm_test_get_num_images(p_hwfn, p_ptt, &num_images);
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rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, p_ptt, &num_images);
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if (rc || !num_images) {
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DP_ERR(p_hwfn, "Failed getting number of images\n");
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return -EINVAL;
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@ -136,8 +136,8 @@ int qed_selftest_nvram(struct qed_dev *cdev)
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/* This mailbox returns information about the image required for
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* reading it.
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*/
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rc = qed_mcp_bist_nvm_test_get_image_att(p_hwfn, p_ptt,
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&image_att, i);
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rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
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&image_att, i);
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if (rc) {
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DP_ERR(p_hwfn,
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"Failed getting image index %d attributes\n",
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