mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 08:46:40 +07:00
Xtensa improvements for v4.19:
- switch xtensa arch to the generic noncoherent direct mapping operations; - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute; - clean up users of platform/hardware.h in generic Xtensa code; - fix assembly cache maintenance code for long cache lines; - rework noMMU cache attributes initialization; - add big-endian HiFi2 test_kc705_be CPU variant. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlt7KZATHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRKZyD/9hJ9L4qNa+E1UaEGxuLcQP98HtwXDV 140/v8m6pw3leblyIGiFypnjHZidol74YQ17DDzckEuSZLa13H8EcB1c/oNTjKve 65/Jz8M9KPaASIRgdcqMp7IZt4wGSVV4mOkwodtmJBefpQa6Y2gHXhmLiIK27WVR m/J6xVYCgTa93e+Tjcn1x+Y1NbpzFlRV2MTfMZLD8hxtUYmt+iPPUtWMKjn3bBJI ps0cor1yAvbGQ6Bg95yal/Wd6pHfnqMs3is3BqW4ZC0LYwch+JT5Btbh2SVYOrX+ ea7iAy3f8eH866SAGb4B3JOTwtaSFL84QFVp/UXY0tZk2IDr3YGiBOV2pic2zSao 3td3y/ZTROcW+18gUip5VtaSKbVZ1yWbut9MnbW2i79VoXAx3XwA4Mo9cBYTQUaj rAB/B62ACcQt0OUG4jvamGdmIgF+FF6Pr4nqJ9iFfIoj4e+UxUMH9U2Wd8H/7WCl rWYJEIkGE8z7bkQw2izXfVc3wBSc2c6z3UjEMijU8I7/V3Yg+WKcAgaWsHd34IDS bURrTWqPN4plXbuuQHrRinHlFUjsx6iZk3ClXn7NTFPx2G69aPOoiHxz0tV9C9Tp fwRHMy5wTeKjfbz4Gd2LlHjDz6kO53DVOsb09B12lVPPTvtLOLbI0G4gHzOw3QVk WwxmbsAv1/NaLA== =osJd -----END PGP SIGNATURE----- Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa Pull Xtensa updates from Max Filippov: - switch xtensa arch to the generic noncoherent direct mapping operations - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute - clean up users of platform/hardware.h in generic Xtensa code - fix assembly cache maintenance code for long cache lines - rework noMMU cache attributes initialization - add big-endian HiFi2 test_kc705_be CPU variant * tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: add test_kc705_be variant xtensa: clean up boot-elf/bootstrap.S xtensa: make bootparam parsing optional xtensa: drop variant IRQ support xtensa: drop unneeded platform/hardware.h headers xtensa: move PLATFORM_NR_IRQS to Kconfig xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE xtensa: rework noMMU cache attributes initialization xtensa: increase ranges in ___invalidate_{i,d}cache_all xtensa: limit offsets in __loop_cache_{all,page} xtensa: platform-specific handling of coherent memory xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute xtensa: use generic dma_noncoherent_ops
This commit is contained in:
commit
433bcf6737
@ -4,12 +4,15 @@ config ZONE_DMA
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config XTENSA
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def_bool y
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_NO_COHERENT_DMA_MMAP if !MMU
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select ARCH_WANT_FRAME_POINTERS
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select ARCH_WANT_IPC_PARSE_VERSION
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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select DMA_NONCOHERENT_OPS
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_SHOW
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@ -72,9 +75,6 @@ config TRACE_IRQFLAGS_SUPPORT
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config MMU
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def_bool n
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config VARIANT_IRQ_SWITCH
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def_bool n
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config HAVE_XTENSA_GPIO32
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def_bool n
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@ -244,6 +244,23 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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If in doubt, say Y.
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config MEMMAP_CACHEATTR
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hex "Cache attributes for the memory address space"
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depends on !MMU
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default 0x22222222
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help
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These cache attributes are set up for noMMU systems. Each hex digit
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specifies cache attributes for the corresponding 512MB memory
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region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
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bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
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Cache attribute values are specific for the MMU type, so e.g.
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for region protection MMUs: 2 is cache bypass, 4 is WB cached,
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1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,
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bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,
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1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is
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reserved).
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config KSEG_PADDR
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hex "Physical address of the KSEG mapping"
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depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
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@ -413,6 +430,10 @@ config XTENSA_PLATFORM_XTFPGA
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endchoice
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config PLATFORM_NR_IRQS
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int
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default 3 if XTENSA_PLATFORM_XT2000
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default 0
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config XTENSA_CPU_CLOCK
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int "CPU clock rate [MHz]"
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@ -450,6 +471,15 @@ config BUILTIN_DTB
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string "DTB to build into the kernel image"
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depends on OF
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config PARSE_BOOTPARAM
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bool "Parse bootparam block"
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default y
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help
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Parse parameters passed to the kernel from the bootloader. It may
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be disabled if the kernel is known to run without the bootloader.
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If unsure, say Y.
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config BLK_DEV_SIMDISK
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tristate "Host file-based simulated block device support"
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default n
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@ -506,25 +536,13 @@ config PLATFORM_WANT_DEFAULT_MEM
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def_bool n
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config DEFAULT_MEM_START
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hex "Physical address of the default memory area start"
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depends on PLATFORM_WANT_DEFAULT_MEM
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default 0x00000000 if MMU
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default 0x60000000 if !MMU
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hex
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prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
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default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
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default 0x00000000
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help
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This is the base address of the default memory area.
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Default memory area has platform-specific meaning, it may be used
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for e.g. early cache initialization.
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If unsure, leave the default value here.
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config DEFAULT_MEM_SIZE
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hex "Maximal size of the default memory area"
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depends on PLATFORM_WANT_DEFAULT_MEM
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default 0x04000000
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help
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This is the size of the default memory area.
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Default memory area has platform-specific meaning, it may be used
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for e.g. early cache initialization.
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This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
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in noMMU configurations.
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If unsure, leave the default value here.
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@ -15,10 +15,6 @@
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*/
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#include <asm/bootparam.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/cacheasm.h>
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#include <asm/initialize_mmu.h>
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#include <asm/vectors.h>
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#include <linux/linkage.h>
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@ -33,16 +29,18 @@ _ResetVector:
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.begin no-absolute-literals
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.literal_position
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.align 4
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RomInitAddr:
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#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
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XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
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.word CONFIG_KERNEL_LOAD_ADDRESS
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.literal RomInitAddr, CONFIG_KERNEL_LOAD_ADDRESS
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#else
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.word KERNELOFFSET
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.literal RomInitAddr, KERNELOFFSET
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#endif
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RomBootParam:
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.word _bootparam
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#ifndef CONFIG_PARSE_BOOTPARAM
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.literal RomBootParam, 0
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#else
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.literal RomBootParam, _bootparam
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.align 4
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_bootparam:
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.short BP_TAG_FIRST
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.short 4
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@ -50,6 +48,7 @@ _bootparam:
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.short BP_TAG_LAST
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.short 0
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.long 0
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#endif
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.align 4
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_SetupMMU:
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@ -33,13 +33,13 @@ CONFIG_XTENSA_VARIANT_CUSTOM_NAME="de212"
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# CONFIG_XTENSA_VARIANT_MMU is not set
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CONFIG_XTENSA_UNALIGNED_USER=y
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CONFIG_PREEMPT=y
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CONFIG_MEMMAP_CACHEATTR=0xfff2442f
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# CONFIG_PCI is not set
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CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000"
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="kc705_nommu"
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CONFIG_DEFAULT_MEM_SIZE=0x10000000
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CONFIG_BINFMT_FLAT=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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@ -3,6 +3,7 @@ generic-y += compat.h
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generic-y += device.h
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generic-y += div64.h
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generic-y += dma-contiguous.h
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generic-y += dma-mapping.h
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generic-y += emergency-restart.h
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generic-y += exec.h
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generic-y += extable.h
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@ -31,16 +31,32 @@
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*
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*/
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.macro __loop_cache_all ar at insn size line_width
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.macro __loop_cache_unroll ar at insn size line_width max_immed
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.if (1 << (\line_width)) > (\max_immed)
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.set _reps, 1
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.elseif (2 << (\line_width)) > (\max_immed)
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.set _reps, 2
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.else
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.set _reps, 4
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.endif
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__loopi \ar, \at, \size, (_reps << (\line_width))
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.set _index, 0
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.rep _reps
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\insn \ar, _index << (\line_width)
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.set _index, _index + 1
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.endr
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__endla \ar, \at, _reps << (\line_width)
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.endm
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.macro __loop_cache_all ar at insn size line_width max_immed
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movi \ar, 0
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__loopi \ar, \at, \size, (4 << (\line_width))
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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__loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed
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.endm
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@ -57,14 +73,9 @@
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.endm
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.macro __loop_cache_page ar at insn line_width
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.macro __loop_cache_page ar at insn line_width max_immed
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__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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__loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed
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.endm
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@ -72,7 +83,8 @@
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.macro ___unlock_dcache_all ar at
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#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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@ -81,7 +93,8 @@
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.macro ___unlock_icache_all ar at
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#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
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__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
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XCHAL_ICACHE_LINEWIDTH 240
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#endif
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.endm
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@ -90,7 +103,8 @@
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.macro ___flush_invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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@ -99,7 +113,8 @@
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.macro ___flush_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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@ -108,8 +123,8 @@
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.macro ___invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
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XCHAL_DCACHE_LINEWIDTH
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__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 1020
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#endif
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.endm
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@ -118,8 +133,8 @@
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.macro ___invalidate_icache_all ar at
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#if XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
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XCHAL_ICACHE_LINEWIDTH
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__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
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XCHAL_ICACHE_LINEWIDTH 1020
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#endif
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.endm
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@ -166,7 +181,7 @@
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.macro ___flush_invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
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__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
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#endif
|
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|
||||
.endm
|
||||
@ -175,7 +190,7 @@
|
||||
.macro ___flush_dcache_page ar as
|
||||
|
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#if XCHAL_DCACHE_SIZE
|
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__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
|
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__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
|
||||
#endif
|
||||
|
||||
.endm
|
||||
@ -184,7 +199,7 @@
|
||||
.macro ___invalidate_dcache_page ar as
|
||||
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
|
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__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
|
||||
#endif
|
||||
|
||||
.endm
|
||||
@ -193,7 +208,7 @@
|
||||
.macro ___invalidate_icache_page ar as
|
||||
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
|
||||
__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
|
||||
#endif
|
||||
|
||||
.endm
|
||||
|
@ -1,26 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003 - 2005 Tensilica Inc.
|
||||
* Copyright (C) 2015 Cadence Design Systems Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_DMA_MAPPING_H
|
||||
#define _XTENSA_DMA_MAPPING_H
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
extern const struct dma_map_ops xtensa_dma_map_ops;
|
||||
|
||||
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
|
||||
{
|
||||
return &xtensa_dma_map_ops;
|
||||
}
|
||||
|
||||
#endif /* _XTENSA_DMA_MAPPING_H */
|
@ -177,36 +177,36 @@
|
||||
#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
|
||||
XCHAL_HAVE_SPANNING_WAY */
|
||||
|
||||
#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
|
||||
(XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
|
||||
/* Enable data and instruction cache in the DEFAULT_MEMORY region
|
||||
* if the processor has DTLB and ITLB.
|
||||
*/
|
||||
.endm
|
||||
|
||||
movi a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY
|
||||
.macro initialize_cacheattr
|
||||
|
||||
#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
|
||||
#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU
|
||||
#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.
|
||||
#endif
|
||||
|
||||
movi a5, XCHAL_SPANNING_WAY
|
||||
movi a6, ~_PAGE_ATTRIB_MASK
|
||||
movi a7, CA_WRITEBACK
|
||||
movi a4, CONFIG_MEMMAP_CACHEATTR
|
||||
movi a8, 0x20000000
|
||||
movi a9, PLATFORM_DEFAULT_MEM_SIZE
|
||||
j 2f
|
||||
1:
|
||||
sub a9, a9, a8
|
||||
2:
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
rdtlb1 a3, a5
|
||||
xor a3, a3, a4
|
||||
and a3, a3, a6
|
||||
or a3, a3, a7
|
||||
xor a3, a3, a4
|
||||
wdtlb a3, a5
|
||||
#endif
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
ritlb1 a4, a5
|
||||
and a4, a4, a6
|
||||
or a4, a4, a7
|
||||
witlb a4, a5
|
||||
#endif
|
||||
add a5, a5, a8
|
||||
bltu a8, a9, 1b
|
||||
ritlb1 a3, a5
|
||||
xor a3, a3, a4
|
||||
and a3, a3, a6
|
||||
xor a3, a3, a4
|
||||
witlb a3, a5
|
||||
|
||||
add a5, a5, a8
|
||||
srli a4, a4, 4
|
||||
bgeu a5, a8, 1b
|
||||
|
||||
isync
|
||||
#endif
|
||||
|
||||
.endm
|
||||
|
@ -12,32 +12,17 @@
|
||||
#define _XTENSA_IRQ_H
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <platform/hardware.h>
|
||||
#include <variant/core.h>
|
||||
|
||||
#ifdef CONFIG_VARIANT_IRQ_SWITCH
|
||||
#include <variant/irq.h>
|
||||
#ifdef CONFIG_PLATFORM_NR_IRQS
|
||||
# define PLATFORM_NR_IRQS CONFIG_PLATFORM_NR_IRQS
|
||||
#else
|
||||
static inline void variant_irq_enable(unsigned int irq) { }
|
||||
static inline void variant_irq_disable(unsigned int irq) { }
|
||||
#endif
|
||||
|
||||
#ifndef VARIANT_NR_IRQS
|
||||
# define VARIANT_NR_IRQS 0
|
||||
#endif
|
||||
#ifndef PLATFORM_NR_IRQS
|
||||
# define PLATFORM_NR_IRQS 0
|
||||
#endif
|
||||
#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
|
||||
#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS + 1)
|
||||
#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS + 1)
|
||||
#define XTENSA_PIC_LINUX_IRQ(hwirq) ((hwirq) + 1)
|
||||
|
||||
#if VARIANT_NR_IRQS == 0
|
||||
static inline void variant_init_irq(void) { }
|
||||
#else
|
||||
void variant_init_irq(void) __init;
|
||||
#endif
|
||||
|
||||
static __inline__ int irq_canonicalize(int irq)
|
||||
{
|
||||
return (irq);
|
||||
|
@ -63,12 +63,6 @@
|
||||
#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
|
||||
#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
|
||||
#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_KASAN
|
||||
|
@ -14,7 +14,6 @@
|
||||
#include <asm/processor.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/cache.h>
|
||||
#include <platform/hardware.h>
|
||||
#include <asm/kmem_layout.h>
|
||||
|
||||
/*
|
||||
@ -31,8 +30,8 @@
|
||||
#define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \
|
||||
PHYS_PFN(XCHAL_KSEG_SIZE))
|
||||
#else
|
||||
#define PAGE_OFFSET PLATFORM_DEFAULT_MEM_START
|
||||
#define PHYS_OFFSET PLATFORM_DEFAULT_MEM_START
|
||||
#define PAGE_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
|
||||
#define PHYS_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
|
||||
#define MAX_LOW_PFN PHYS_PFN(0xfffffffful)
|
||||
#endif
|
||||
|
||||
|
@ -66,6 +66,7 @@
|
||||
#define FIRST_USER_ADDRESS 0UL
|
||||
#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
/*
|
||||
* Virtual memory area. We keep a distance to other memory regions to be
|
||||
* on the safe side. We also use this area for cache aliasing.
|
||||
@ -80,6 +81,13 @@
|
||||
#define TLBTEMP_SIZE ICACHE_WAY_SIZE
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define VMALLOC_START __XTENSA_UL_CONST(0)
|
||||
#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* For the Xtensa architecture, the PTE layout is as follows:
|
||||
*
|
||||
|
@ -75,4 +75,31 @@ extern void platform_calibrate_ccount (void);
|
||||
*/
|
||||
void cpu_reset(void) __attribute__((noreturn));
|
||||
|
||||
/*
|
||||
* Memory caching is platform-dependent in noMMU xtensa configurations.
|
||||
* The following set of functions should be implemented in platform code
|
||||
* in order to enable coherent DMA memory operations when CONFIG_MMU is not
|
||||
* enabled. Default implementations do nothing and issue a warning.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Check whether p points to a cached memory.
|
||||
*/
|
||||
bool platform_vaddr_cached(const void *p);
|
||||
|
||||
/*
|
||||
* Check whether p points to an uncached memory.
|
||||
*/
|
||||
bool platform_vaddr_uncached(const void *p);
|
||||
|
||||
/*
|
||||
* Return pointer to an uncached view of the cached sddress p.
|
||||
*/
|
||||
void *platform_vaddr_to_uncached(void *p);
|
||||
|
||||
/*
|
||||
* Return pointer to a cached view of the uncached sddress p.
|
||||
*/
|
||||
void *platform_vaddr_to_cached(void *p);
|
||||
|
||||
#endif /* _XTENSA_PLATFORM_H */
|
||||
|
@ -11,7 +11,6 @@
|
||||
#define _XTENSA_PROCESSOR_H
|
||||
|
||||
#include <variant/core.h>
|
||||
#include <platform/hardware.h>
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
@ -19,7 +19,6 @@
|
||||
#define _XTENSA_VECTORS_H
|
||||
|
||||
#include <variant/core.h>
|
||||
#include <platform/hardware.h>
|
||||
#include <asm/kmem_layout.h>
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
|
@ -181,6 +181,8 @@ ENTRY(_startup)
|
||||
|
||||
isync
|
||||
|
||||
initialize_cacheattr
|
||||
|
||||
#ifdef CONFIG_HAVE_SMP
|
||||
movi a2, CCON # MX External Register to Configure Cache
|
||||
movi a3, 1
|
||||
|
@ -158,7 +158,6 @@ void __init init_IRQ(void)
|
||||
#ifdef CONFIG_SMP
|
||||
ipi_init();
|
||||
#endif
|
||||
variant_init_irq();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
@ -16,26 +16,25 @@
|
||||
*/
|
||||
|
||||
#include <linux/dma-contiguous.h>
|
||||
#include <linux/dma-noncoherent.h>
|
||||
#include <linux/dma-direct.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/platform.h>
|
||||
|
||||
static void do_cache_op(dma_addr_t dma_handle, size_t size,
|
||||
static void do_cache_op(phys_addr_t paddr, size_t size,
|
||||
void (*fn)(unsigned long, unsigned long))
|
||||
{
|
||||
unsigned long off = dma_handle & (PAGE_SIZE - 1);
|
||||
unsigned long pfn = PFN_DOWN(dma_handle);
|
||||
unsigned long off = paddr & (PAGE_SIZE - 1);
|
||||
unsigned long pfn = PFN_DOWN(paddr);
|
||||
struct page *page = pfn_to_page(pfn);
|
||||
|
||||
if (!PageHighMem(page))
|
||||
fn((unsigned long)bus_to_virt(dma_handle), size);
|
||||
fn((unsigned long)phys_to_virt(paddr), size);
|
||||
else
|
||||
while (size > 0) {
|
||||
size_t sz = min_t(size_t, size, PAGE_SIZE - off);
|
||||
@ -49,14 +48,13 @@ static void do_cache_op(dma_addr_t dma_handle, size_t size,
|
||||
}
|
||||
}
|
||||
|
||||
static void xtensa_sync_single_for_cpu(struct device *dev,
|
||||
dma_addr_t dma_handle, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
switch (dir) {
|
||||
case DMA_BIDIRECTIONAL:
|
||||
case DMA_FROM_DEVICE:
|
||||
do_cache_op(dma_handle, size, __invalidate_dcache_range);
|
||||
do_cache_op(paddr, size, __invalidate_dcache_range);
|
||||
break;
|
||||
|
||||
case DMA_NONE:
|
||||
@ -68,15 +66,14 @@ static void xtensa_sync_single_for_cpu(struct device *dev,
|
||||
}
|
||||
}
|
||||
|
||||
static void xtensa_sync_single_for_device(struct device *dev,
|
||||
dma_addr_t dma_handle, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
switch (dir) {
|
||||
case DMA_BIDIRECTIONAL:
|
||||
case DMA_TO_DEVICE:
|
||||
if (XCHAL_DCACHE_IS_WRITEBACK)
|
||||
do_cache_op(dma_handle, size, __flush_dcache_range);
|
||||
do_cache_op(paddr, size, __flush_dcache_range);
|
||||
break;
|
||||
|
||||
case DMA_NONE:
|
||||
@ -88,43 +85,66 @@ static void xtensa_sync_single_for_device(struct device *dev,
|
||||
}
|
||||
}
|
||||
|
||||
static void xtensa_sync_sg_for_cpu(struct device *dev,
|
||||
struct scatterlist *sg, int nents,
|
||||
enum dma_data_direction dir)
|
||||
#ifdef CONFIG_MMU
|
||||
bool platform_vaddr_cached(const void *p)
|
||||
{
|
||||
struct scatterlist *s;
|
||||
int i;
|
||||
unsigned long addr = (unsigned long)p;
|
||||
|
||||
for_each_sg(sg, s, nents, i) {
|
||||
xtensa_sync_single_for_cpu(dev, sg_dma_address(s),
|
||||
sg_dma_len(s), dir);
|
||||
}
|
||||
return addr >= XCHAL_KSEG_CACHED_VADDR &&
|
||||
addr - XCHAL_KSEG_CACHED_VADDR < XCHAL_KSEG_SIZE;
|
||||
}
|
||||
|
||||
static void xtensa_sync_sg_for_device(struct device *dev,
|
||||
struct scatterlist *sg, int nents,
|
||||
enum dma_data_direction dir)
|
||||
bool platform_vaddr_uncached(const void *p)
|
||||
{
|
||||
struct scatterlist *s;
|
||||
int i;
|
||||
unsigned long addr = (unsigned long)p;
|
||||
|
||||
for_each_sg(sg, s, nents, i) {
|
||||
xtensa_sync_single_for_device(dev, sg_dma_address(s),
|
||||
sg_dma_len(s), dir);
|
||||
}
|
||||
return addr >= XCHAL_KSEG_BYPASS_VADDR &&
|
||||
addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE;
|
||||
}
|
||||
|
||||
void *platform_vaddr_to_uncached(void *p)
|
||||
{
|
||||
return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
|
||||
}
|
||||
|
||||
void *platform_vaddr_to_cached(void *p)
|
||||
{
|
||||
return p + XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
|
||||
}
|
||||
#else
|
||||
bool __attribute__((weak)) platform_vaddr_cached(const void *p)
|
||||
{
|
||||
WARN_ONCE(1, "Default %s implementation is used\n", __func__);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool __attribute__((weak)) platform_vaddr_uncached(const void *p)
|
||||
{
|
||||
WARN_ONCE(1, "Default %s implementation is used\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
void __attribute__((weak)) *platform_vaddr_to_uncached(void *p)
|
||||
{
|
||||
WARN_ONCE(1, "Default %s implementation is used\n", __func__);
|
||||
return p;
|
||||
}
|
||||
|
||||
void __attribute__((weak)) *platform_vaddr_to_cached(void *p)
|
||||
{
|
||||
WARN_ONCE(1, "Default %s implementation is used\n", __func__);
|
||||
return p;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Note: We assume that the full memory space is always mapped to 'kseg'
|
||||
* Otherwise we have to use page attributes (not implemented).
|
||||
*/
|
||||
|
||||
static void *xtensa_dma_alloc(struct device *dev, size_t size,
|
||||
dma_addr_t *handle, gfp_t flag,
|
||||
unsigned long attrs)
|
||||
void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
|
||||
gfp_t flag, unsigned long attrs)
|
||||
{
|
||||
unsigned long ret;
|
||||
unsigned long uncached;
|
||||
unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
||||
struct page *page = NULL;
|
||||
|
||||
@ -147,6 +167,10 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
|
||||
|
||||
*handle = phys_to_dma(dev, page_to_phys(page));
|
||||
|
||||
if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
|
||||
return page;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
if (PageHighMem(page)) {
|
||||
void *p;
|
||||
@ -161,27 +185,21 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
|
||||
return p;
|
||||
}
|
||||
#endif
|
||||
ret = (unsigned long)page_address(page);
|
||||
BUG_ON(ret < XCHAL_KSEG_CACHED_VADDR ||
|
||||
ret > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1);
|
||||
|
||||
uncached = ret + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
|
||||
__invalidate_dcache_range(ret, size);
|
||||
|
||||
return (void *)uncached;
|
||||
BUG_ON(!platform_vaddr_cached(page_address(page)));
|
||||
__invalidate_dcache_range((unsigned long)page_address(page), size);
|
||||
return platform_vaddr_to_uncached(page_address(page));
|
||||
}
|
||||
|
||||
static void xtensa_dma_free(struct device *dev, size_t size, void *vaddr,
|
||||
dma_addr_t dma_handle, unsigned long attrs)
|
||||
void arch_dma_free(struct device *dev, size_t size, void *vaddr,
|
||||
dma_addr_t dma_handle, unsigned long attrs)
|
||||
{
|
||||
unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
||||
unsigned long addr = (unsigned long)vaddr;
|
||||
struct page *page;
|
||||
|
||||
if (addr >= XCHAL_KSEG_BYPASS_VADDR &&
|
||||
addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE) {
|
||||
addr += XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
|
||||
page = virt_to_page(addr);
|
||||
if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
|
||||
page = vaddr;
|
||||
} else if (platform_vaddr_uncached(vaddr)) {
|
||||
page = virt_to_page(platform_vaddr_to_cached(vaddr));
|
||||
} else {
|
||||
#ifdef CONFIG_MMU
|
||||
dma_common_free_remap(vaddr, size, VM_MAP);
|
||||
@ -192,72 +210,3 @@ static void xtensa_dma_free(struct device *dev, size_t size, void *vaddr,
|
||||
if (!dma_release_from_contiguous(dev, page, count))
|
||||
__free_pages(page, get_order(size));
|
||||
}
|
||||
|
||||
static dma_addr_t xtensa_map_page(struct device *dev, struct page *page,
|
||||
unsigned long offset, size_t size,
|
||||
enum dma_data_direction dir,
|
||||
unsigned long attrs)
|
||||
{
|
||||
dma_addr_t dma_handle = page_to_phys(page) + offset;
|
||||
|
||||
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
|
||||
xtensa_sync_single_for_device(dev, dma_handle, size, dir);
|
||||
|
||||
return dma_handle;
|
||||
}
|
||||
|
||||
static void xtensa_unmap_page(struct device *dev, dma_addr_t dma_handle,
|
||||
size_t size, enum dma_data_direction dir,
|
||||
unsigned long attrs)
|
||||
{
|
||||
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
|
||||
xtensa_sync_single_for_cpu(dev, dma_handle, size, dir);
|
||||
}
|
||||
|
||||
static int xtensa_map_sg(struct device *dev, struct scatterlist *sg,
|
||||
int nents, enum dma_data_direction dir,
|
||||
unsigned long attrs)
|
||||
{
|
||||
struct scatterlist *s;
|
||||
int i;
|
||||
|
||||
for_each_sg(sg, s, nents, i) {
|
||||
s->dma_address = xtensa_map_page(dev, sg_page(s), s->offset,
|
||||
s->length, dir, attrs);
|
||||
}
|
||||
return nents;
|
||||
}
|
||||
|
||||
static void xtensa_unmap_sg(struct device *dev,
|
||||
struct scatterlist *sg, int nents,
|
||||
enum dma_data_direction dir,
|
||||
unsigned long attrs)
|
||||
{
|
||||
struct scatterlist *s;
|
||||
int i;
|
||||
|
||||
for_each_sg(sg, s, nents, i) {
|
||||
xtensa_unmap_page(dev, sg_dma_address(s),
|
||||
sg_dma_len(s), dir, attrs);
|
||||
}
|
||||
}
|
||||
|
||||
int xtensa_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct dma_map_ops xtensa_dma_map_ops = {
|
||||
.alloc = xtensa_dma_alloc,
|
||||
.free = xtensa_dma_free,
|
||||
.map_page = xtensa_map_page,
|
||||
.unmap_page = xtensa_unmap_page,
|
||||
.map_sg = xtensa_map_sg,
|
||||
.unmap_sg = xtensa_unmap_sg,
|
||||
.sync_single_for_cpu = xtensa_sync_single_for_cpu,
|
||||
.sync_single_for_device = xtensa_sync_single_for_device,
|
||||
.sync_sg_for_cpu = xtensa_sync_sg_for_cpu,
|
||||
.sync_sg_for_device = xtensa_sync_sg_for_device,
|
||||
.mapping_error = xtensa_dma_mapping_error,
|
||||
};
|
||||
EXPORT_SYMBOL(xtensa_dma_map_ops);
|
||||
|
@ -47,8 +47,6 @@
|
||||
#include <asm/smp.h>
|
||||
#include <asm/sysmem.h>
|
||||
|
||||
#include <platform/hardware.h>
|
||||
|
||||
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
|
||||
struct screen_info screen_info = {
|
||||
.orig_x = 0,
|
||||
@ -81,6 +79,7 @@ static char __initdata command_line[COMMAND_LINE_SIZE];
|
||||
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PARSE_BOOTPARAM
|
||||
/*
|
||||
* Boot parameter parsing.
|
||||
*
|
||||
@ -178,6 +177,13 @@ static int __init parse_bootparam(const bp_tag_t* tag)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int __init parse_bootparam(const bp_tag_t *tag)
|
||||
{
|
||||
pr_info("Ignoring boot parameters at %p\n", tag);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
|
@ -20,7 +20,7 @@
|
||||
|
||||
#include <asm/vectors.h>
|
||||
#include <variant/core.h>
|
||||
#include <platform/hardware.h>
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
ENTRY(_start)
|
||||
|
||||
|
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* include/asm-xtensa/platform-iss/hardware.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Tensilica Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the default configuration of ISS.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_PLATFORM_ISS_HARDWARE_H
|
||||
#define _XTENSA_PLATFORM_ISS_HARDWARE_H
|
||||
|
||||
/*
|
||||
* Memory configuration.
|
||||
*/
|
||||
|
||||
#define PLATFORM_DEFAULT_MEM_START 0x00000000
|
||||
#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
|
||||
|
||||
/*
|
||||
* Interrupt configuration.
|
||||
*/
|
||||
|
||||
#endif /* _XTENSA_PLATFORM_ISS_HARDWARE_H */
|
@ -17,17 +17,6 @@
|
||||
|
||||
#include <variant/core.h>
|
||||
|
||||
/*
|
||||
* Memory configuration.
|
||||
*/
|
||||
|
||||
#define PLATFORM_DEFAULT_MEM_START 0x00000000
|
||||
#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
|
||||
|
||||
/*
|
||||
* Number of platform IRQs
|
||||
*/
|
||||
#define PLATFORM_NR_IRQS 3
|
||||
/*
|
||||
* On-board components.
|
||||
*/
|
||||
|
@ -17,15 +17,6 @@
|
||||
#ifndef __XTENSA_XTAVNET_HARDWARE_H
|
||||
#define __XTENSA_XTAVNET_HARDWARE_H
|
||||
|
||||
/* Memory configuration. */
|
||||
|
||||
#define PLATFORM_DEFAULT_MEM_START __XTENSA_UL(CONFIG_DEFAULT_MEM_START)
|
||||
#define PLATFORM_DEFAULT_MEM_SIZE __XTENSA_UL(CONFIG_DEFAULT_MEM_SIZE)
|
||||
|
||||
/* Interrupt configuration. */
|
||||
|
||||
#define PLATFORM_NR_IRQS 0
|
||||
|
||||
/* Default assignment of LX60 devices to external interrupts. */
|
||||
|
||||
#ifdef CONFIG_XTENSA_MX
|
||||
|
575
arch/xtensa/variants/test_kc705_be/include/variant/core.h
Normal file
575
arch/xtensa/variants/test_kc705_be/include/variant/core.h
Normal file
@ -0,0 +1,575 @@
|
||||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2015 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
|
||||
#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "test_kc705_be" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00058D8C /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC1B3FFFF /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1C858D8C /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260002 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_2 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 8
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
/* Whether MEMCTL register has anything useful */
|
||||
#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
|
||||
XCHAL_DCACHE_IS_COHERENT || \
|
||||
XCHAL_HAVE_ICACHE_DYN_WAYS || \
|
||||
XCHAL_HAVE_DCACHE_DYN_WAYS) && \
|
||||
(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000140
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00008000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00003000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 2
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 5
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 4
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00008000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL4_NUM 15
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 5.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 5) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x00002340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00002340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
308
arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h
Normal file
308
arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h
Normal file
@ -0,0 +1,308 @@
|
||||
/*
|
||||
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file contains assembly-language definitions (assembly
|
||||
macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
and options. It is customized to this Xtensa processor configuration.
|
||||
|
||||
Copyright (c) 1999-2015 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_ASM_H
|
||||
#define _XTENSA_CORE_TIE_ASM_H
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
|
||||
| ((ccuse) & XTHAL_SAS_ANYCC) \
|
||||
| ((abi) & XTHAL_SAS_ANYABI) )
|
||||
|
||||
|
||||
/*
|
||||
* Macro to store all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger store sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to store. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to store, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any store.
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
rur.THREADPTR \at1 // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rsr.ACCLO \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.ACCHI \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
rsr.BR \at1 // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.SCOMPARE1 \at1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rsr.M0 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rsr.M1 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rsr.M2 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rsr.M3 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/*
|
||||
* Macro to load all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger load sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to load. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to load, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any load.
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.THREADPTR \at1 // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.ACCLO \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.ACCHI \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.BR \at1 // boolean option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.SCOMPARE1 \at1 // conditional store option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wsr.M0 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wsr.M1 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wsr.M2 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wsr.M3 \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor AudioEngineLX.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 8 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_store xchal_cp1_store
|
||||
.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
rur.AE_OVF_SAR \at1 // ureg 240
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.AE_BITHEAD \at1 // ureg 241
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rur.AE_TS_FTS_BU_BP \at1 // ureg 242
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rur.AE_SD_NO \at1 // ureg 243
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rur.AE_CBEGIN0 \at1 // ureg 246
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rur.AE_CEND0 \at1 // ureg 247
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+24
|
||||
ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+32
|
||||
ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+40
|
||||
ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+48
|
||||
ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+0
|
||||
ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+8
|
||||
ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+16
|
||||
ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+24
|
||||
ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+32
|
||||
ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+40
|
||||
ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+48
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 64
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 120
|
||||
.endif
|
||||
.endm // xchal_cp1_store
|
||||
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor AudioEngineLX.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 8 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_load xchal_cp1_load
|
||||
.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.AE_OVF_SAR \at1 // ureg 240
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.AE_BITHEAD \at1 // ureg 241
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wur.AE_TS_FTS_BU_BP \at1 // ureg 242
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wur.AE_SD_NO \at1 // ureg 243
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wur.AE_CBEGIN0 \at1 // ureg 246
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wur.AE_CEND0 \at1 // ureg 247
|
||||
ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+24
|
||||
ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+32
|
||||
ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+40
|
||||
ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+48
|
||||
ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+0
|
||||
ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+8
|
||||
ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+16
|
||||
addi \ptr, \ptr, 24
|
||||
ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
|
||||
ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
|
||||
ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
|
||||
ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 88
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 32
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 120
|
||||
.endif
|
||||
.endm // xchal_cp1_load
|
||||
|
||||
#define XCHAL_CP1_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
182
arch/xtensa/variants/test_kc705_be/include/variant/tie.h
Normal file
182
arch/xtensa/variants/test_kc705_be/include/variant/tie.h
Normal file
@ -0,0 +1,182 @@
|
||||
/*
|
||||
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file describes this specific Xtensa processor's TIE extensions
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Copyright (c) 1999-2015 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 2 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP1_NAME "AudioEngineLX"
|
||||
#define XCHAL_CP1_IDENT AudioEngineLX
|
||||
#define XCHAL_CP1_SA_SIZE 120 /* size of state save area */
|
||||
#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP7_NAME "XTIOP"
|
||||
#define XCHAL_CP7_IDENT XTIOP
|
||||
#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
|
||||
#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP0_SA_SIZE 0
|
||||
#define XCHAL_CP0_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 36
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 9
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 0
|
||||
#define XCHAL_CP0_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 18
|
||||
#define XCHAL_CP1_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
@ -98,14 +98,12 @@ static void xtensa_mx_irq_unmask(struct irq_data *d)
|
||||
|
||||
static void xtensa_mx_irq_enable(struct irq_data *d)
|
||||
{
|
||||
variant_irq_enable(d->hwirq);
|
||||
xtensa_mx_irq_unmask(d);
|
||||
}
|
||||
|
||||
static void xtensa_mx_irq_disable(struct irq_data *d)
|
||||
{
|
||||
xtensa_mx_irq_mask(d);
|
||||
variant_irq_disable(d->hwirq);
|
||||
}
|
||||
|
||||
static void xtensa_mx_irq_ack(struct irq_data *d)
|
||||
|
@ -55,14 +55,12 @@ static void xtensa_irq_unmask(struct irq_data *d)
|
||||
|
||||
static void xtensa_irq_enable(struct irq_data *d)
|
||||
{
|
||||
variant_irq_enable(d->hwirq);
|
||||
xtensa_irq_unmask(d);
|
||||
}
|
||||
|
||||
static void xtensa_irq_disable(struct irq_data *d)
|
||||
{
|
||||
xtensa_irq_mask(d);
|
||||
variant_irq_disable(d->hwirq);
|
||||
}
|
||||
|
||||
static void xtensa_irq_ack(struct irq_data *d)
|
||||
|
Loading…
Reference in New Issue
Block a user