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[media] cx18: support big-endian systems
base_addr has type resource_size_t, which may be 64 bits. Also fix a few endian issues related to mailboxes and firmware loading. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -838,10 +838,10 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev,
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}
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}
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CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, "
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CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, "
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"irq: %d, latency: %d, memory: 0x%lx\n",
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"irq: %d, latency: %d, memory: 0x%llx\n",
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cx->pci_dev->device, cx->card_rev, pci_dev->bus->number,
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cx->pci_dev->device, cx->card_rev, pci_dev->bus->number,
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PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn),
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PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn),
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cx->pci_dev->irq, pci_latency, (unsigned long)cx->base_addr);
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cx->pci_dev->irq, pci_latency, (u64)cx->base_addr);
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return 0;
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return 0;
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}
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}
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@ -938,7 +938,7 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev,
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if (retval)
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if (retval)
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goto err;
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goto err;
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CX18_DEBUG_INFO("base addr: 0x%08x\n", cx->base_addr);
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CX18_DEBUG_INFO("base addr: 0x%llx\n", (u64)cx->base_addr);
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/* PCI Device Setup */
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/* PCI Device Setup */
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retval = cx18_setup_pci(cx, pci_dev, pci_id);
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retval = cx18_setup_pci(cx, pci_dev, pci_id);
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@ -946,8 +946,8 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev,
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goto free_workqueues;
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goto free_workqueues;
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/* map io memory */
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/* map io memory */
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CX18_DEBUG_INFO("attempting ioremap at 0x%08x len 0x%08x\n",
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CX18_DEBUG_INFO("attempting ioremap at 0x%llx len 0x%08x\n",
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cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE);
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(u64)cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE);
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cx->enc_mem = ioremap_nocache(cx->base_addr + CX18_MEM_OFFSET,
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cx->enc_mem = ioremap_nocache(cx->base_addr + CX18_MEM_OFFSET,
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CX18_MEM_SIZE);
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CX18_MEM_SIZE);
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if (!cx->enc_mem) {
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if (!cx->enc_mem) {
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@ -622,7 +622,7 @@ struct cx18 {
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unique ID. Starts at 1, so 0 can be used as
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unique ID. Starts at 1, so 0 can be used as
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uninitialized value in the stream->id. */
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uninitialized value in the stream->id. */
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u32 base_addr;
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resource_size_t base_addr;
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u8 card_rev;
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u8 card_rev;
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void __iomem *enc_mem, *reg_mem;
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void __iomem *enc_mem, *reg_mem;
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@ -164,8 +164,13 @@ static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
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apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
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apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
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while (offset + sizeof(seghdr) < fw->size) {
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while (offset + sizeof(seghdr) < fw->size) {
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/* TODO: byteswapping */
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const u32 *shptr = src + offset / 4;
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memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
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seghdr.sync1 = le32_to_cpu(shptr[0]);
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seghdr.sync2 = le32_to_cpu(shptr[1]);
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seghdr.addr = le32_to_cpu(shptr[2]);
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seghdr.size = le32_to_cpu(shptr[3]);
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offset += sizeof(seghdr);
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offset += sizeof(seghdr);
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if (seghdr.sync1 != APU_ROM_SYNC1 ||
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if (seghdr.sync1 != APU_ROM_SYNC1 ||
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seghdr.sync2 != APU_ROM_SYNC2) {
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seghdr.sync2 != APU_ROM_SYNC2) {
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@ -434,6 +434,7 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
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{
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{
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u32 handle, mdl_ack_offset, mdl_ack_count;
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u32 handle, mdl_ack_offset, mdl_ack_count;
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struct cx18_mailbox *mb;
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struct cx18_mailbox *mb;
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int i;
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mb = &order->mb;
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mb = &order->mb;
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handle = mb->args[0];
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handle = mb->args[0];
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@ -447,8 +448,9 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
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return -1;
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return -1;
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}
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}
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cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
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for (i = 0; i < sizeof(struct cx18_mdl_ack) * mdl_ack_count; i += sizeof(u32))
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sizeof(struct cx18_mdl_ack) * mdl_ack_count);
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((u32 *)order->mdl_ack)[i / sizeof(u32)] =
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cx18_readl(cx, cx->enc_mem + mdl_ack_offset + i);
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if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
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if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
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mb_ack_irq(cx, order);
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mb_ack_irq(cx, order);
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@ -538,6 +540,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
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struct cx18_mailbox *order_mb;
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struct cx18_mailbox *order_mb;
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struct cx18_in_work_order *order;
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struct cx18_in_work_order *order;
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int submit;
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int submit;
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int i;
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switch (rpu) {
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switch (rpu) {
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case CPU:
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case CPU:
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@ -562,10 +565,12 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
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order_mb = &order->mb;
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order_mb = &order->mb;
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/* mb->cmd and mb->args[0] through mb->args[2] */
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/* mb->cmd and mb->args[0] through mb->args[2] */
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cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
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for (i = 0; i < 4; i++)
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(&order_mb->cmd)[i] = cx18_readl(cx, &mb->cmd + i);
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/* mb->request and mb->ack. N.B. we want to read mb->ack last */
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/* mb->request and mb->ack. N.B. we want to read mb->ack last */
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cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
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for (i = 0; i < 2; i++)
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2 * sizeof(u32));
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(&order_mb->request)[i] = cx18_readl(cx, &mb->request + i);
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if (order_mb->request == order_mb->ack) {
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if (order_mb->request == order_mb->ack) {
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CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
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CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
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