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ASoC: meson: axg-fifo: relax period size constraints
Now that the fifo depths and thresholds are properly in the axg-fifo driver, we can relax the constraints on period. As long as the period is a multiple of the fifo burst size (8 bytes) things should be OK. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20191218172420.1199117-5-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -34,7 +34,7 @@ static struct snd_pcm_hardware axg_fifo_hw = {
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.rate_max = 192000,
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.channels_min = 1,
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.channels_max = AXG_FIFO_CH_MAX,
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.period_bytes_min = AXG_FIFO_MIN_DEPTH,
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.period_bytes_min = AXG_FIFO_BURST,
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.period_bytes_max = UINT_MAX,
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.periods_min = 2,
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.periods_max = UINT_MAX,
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@ -227,17 +227,17 @@ int axg_fifo_pcm_open(struct snd_soc_component *component,
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/*
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* Make sure the buffer and period size are multiple of the FIFO
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* minimum depth size
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* burst
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*/
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
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AXG_FIFO_MIN_DEPTH);
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AXG_FIFO_BURST);
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if (ret)
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return ret;
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
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AXG_FIFO_MIN_DEPTH);
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AXG_FIFO_BURST);
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if (ret)
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return ret;
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@ -31,8 +31,6 @@ struct snd_soc_pcm_runtime;
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SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
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#define AXG_FIFO_BURST 8
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#define AXG_FIFO_MIN_CNT 64
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#define AXG_FIFO_MIN_DEPTH (AXG_FIFO_BURST * AXG_FIFO_MIN_CNT)
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#define FIFO_INT_ADDR_FINISH BIT(0)
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#define FIFO_INT_ADDR_INT BIT(1)
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