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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mt76: move mt76x02_mac_write_txwi in mt76x02-lib module
Move mt76x02_mac_write_txwi in mt76x02_mac.c since it is shared between mt76x0 and mt76x2 drivers. This is a preliminary patch to unify txwi configuration between mt76x0 and mt76x2 drivers Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
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1ef3aa8893
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427f9ebec6
@ -18,6 +18,7 @@
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#include "mt76.h"
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#include "mt76.h"
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#include "mt76x02_regs.h"
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#include "mt76x02_regs.h"
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#include "mt76x02_mac.h"
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#include "mt76x02_mac.h"
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#include "mt76x02_util.h"
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enum mt76x02_cipher_type
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enum mt76x02_cipher_type
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mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
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mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
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@ -341,6 +342,68 @@ mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
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return 0;
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return 0;
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}
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}
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void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, int len)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_tx_rate *rate = &info->control.rates[0];
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struct ieee80211_key_conf *key = info->control.hw_key;
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u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
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u8 nss;
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s8 txpwr_adj, max_txpwr_adj;
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u8 ccmp_pn[8], nstreams = dev->chainmask & 0xf;
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memset(txwi, 0, sizeof(*txwi));
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if (wcid)
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txwi->wcid = wcid->idx;
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else
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txwi->wcid = 0xff;
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txwi->pktid = 1;
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if (wcid && wcid->sw_iv && key) {
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u64 pn = atomic64_inc_return(&key->tx_pn);
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ccmp_pn[0] = pn;
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ccmp_pn[1] = pn >> 8;
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ccmp_pn[2] = 0;
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ccmp_pn[3] = 0x20 | (key->keyidx << 6);
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ccmp_pn[4] = pn >> 16;
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ccmp_pn[5] = pn >> 24;
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ccmp_pn[6] = pn >> 32;
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ccmp_pn[7] = pn >> 40;
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txwi->iv = *((__le32 *)&ccmp_pn[0]);
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txwi->eiv = *((__le32 *)&ccmp_pn[1]);
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}
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spin_lock_bh(&dev->lock);
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if (wcid && (rate->idx < 0 || !rate->count)) {
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txwi->rate = wcid->tx_rate;
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max_txpwr_adj = wcid->max_txpwr_adj;
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nss = wcid->tx_rate_nss;
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} else {
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txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss);
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max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
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}
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spin_unlock_bh(&dev->lock);
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if (dev->drv->get_tx_txpwr_adj) {
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txpwr_adj = dev->drv->get_tx_txpwr_adj(dev, dev->txpower_conf,
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max_txpwr_adj);
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txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
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}
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if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E4)
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txwi->txstream = 0x13;
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else if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E3 &&
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!(txwi->rate & cpu_to_le16(rate_ht_mask)))
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txwi->txstream = 0x93;
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mt76x02_mac_fill_txwi(txwi, skb, sta, len, nss);
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}
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EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi);
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static void
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static void
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mt76x02_mac_fill_tx_status(struct mt76_dev *dev,
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mt76x02_mac_fill_tx_status(struct mt76_dev *dev,
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struct ieee80211_tx_info *info,
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struct ieee80211_tx_info *info,
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@ -203,4 +203,7 @@ void mt76x02_send_tx_status(struct mt76_dev *dev,
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int
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int
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mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate);
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mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate);
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void mt76x02_mac_setaddr(struct mt76_dev *dev, u8 *addr);
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void mt76x02_mac_setaddr(struct mt76_dev *dev, u8 *addr);
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void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, int len);
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#endif
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#endif
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@ -54,66 +54,6 @@ void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
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}
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}
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EXPORT_SYMBOL_GPL(mt76x2_mac_stop);
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EXPORT_SYMBOL_GPL(mt76x2_mac_stop);
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void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x02_txwi *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, int len)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_tx_rate *rate = &info->control.rates[0];
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struct ieee80211_key_conf *key = info->control.hw_key;
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u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
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u8 nss;
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s8 txpwr_adj, max_txpwr_adj;
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u8 ccmp_pn[8];
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memset(txwi, 0, sizeof(*txwi));
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if (wcid)
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txwi->wcid = wcid->idx;
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else
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txwi->wcid = 0xff;
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txwi->pktid = 1;
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if (wcid && wcid->sw_iv && key) {
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u64 pn = atomic64_inc_return(&key->tx_pn);
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ccmp_pn[0] = pn;
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ccmp_pn[1] = pn >> 8;
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ccmp_pn[2] = 0;
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ccmp_pn[3] = 0x20 | (key->keyidx << 6);
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ccmp_pn[4] = pn >> 16;
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ccmp_pn[5] = pn >> 24;
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ccmp_pn[6] = pn >> 32;
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ccmp_pn[7] = pn >> 40;
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txwi->iv = *((__le32 *)&ccmp_pn[0]);
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txwi->eiv = *((__le32 *)&ccmp_pn[1]);
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}
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spin_lock_bh(&dev->mt76.lock);
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if (wcid && (rate->idx < 0 || !rate->count)) {
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txwi->rate = wcid->tx_rate;
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max_txpwr_adj = wcid->max_txpwr_adj;
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nss = wcid->tx_rate_nss;
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} else {
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txwi->rate = mt76x02_mac_tx_rate_val(&dev->mt76, rate, &nss);
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max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(&dev->mt76, rate);
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}
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spin_unlock_bh(&dev->mt76.lock);
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txpwr_adj = mt76x2_tx_get_txpwr_adj(&dev->mt76, dev->mt76.txpower_conf,
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max_txpwr_adj);
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txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
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if (mt76xx_rev(dev) >= MT76XX_REV_E4)
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txwi->txstream = 0x13;
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else if (mt76xx_rev(dev) >= MT76XX_REV_E3 &&
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!(txwi->rate & cpu_to_le16(rate_ht_mask)))
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txwi->txstream = 0x93;
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mt76x02_mac_fill_txwi(txwi, skb, sta, len, nss);
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}
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EXPORT_SYMBOL_GPL(mt76x2_mac_write_txwi);
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int mt76x2_mac_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain)
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int mt76x2_mac_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain)
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{
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{
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struct mt76x2_rx_freq_cal *cal = &dev->cal.rx;
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struct mt76x2_rx_freq_cal *cal = &dev->cal.rx;
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@ -48,9 +48,6 @@ void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr);
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int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb,
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int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb,
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void *rxi);
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void *rxi);
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void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x02_txwi *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, int len);
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int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx,
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int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx,
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struct sk_buff *skb);
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struct sk_buff *skb);
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@ -106,7 +106,7 @@ mt76_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
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if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi)))
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if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi)))
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return -ENOSPC;
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return -ENOSPC;
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mt76x2_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len);
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mt76x02_mac_write_txwi(&dev->mt76, &txwi, skb, NULL, NULL, skb->len);
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mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
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mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
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offset += sizeof(txwi);
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offset += sizeof(txwi);
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@ -37,7 +37,7 @@ int mt76x2_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
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if (q == &dev->mt76.q_tx[MT_TXQ_PSD] && wcid && wcid->idx < 128)
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if (q == &dev->mt76.q_tx[MT_TXQ_PSD] && wcid && wcid->idx < 128)
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mt76x02_mac_wcid_set_drop(&dev->mt76, wcid->idx, false);
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mt76x02_mac_wcid_set_drop(&dev->mt76, wcid->idx, false);
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mt76x2_mac_write_txwi(dev, txwi, skb, wcid, sta, skb->len);
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mt76x02_mac_write_txwi(mdev, txwi, skb, wcid, sta, skb->len);
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ret = mt76x02_insert_hdr_pad(skb);
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ret = mt76x02_insert_hdr_pad(skb);
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if (ret < 0)
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if (ret < 0)
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@ -36,7 +36,6 @@ int mt76x2u_tx_prepare_skb(struct mt76_dev *mdev, void *data,
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struct mt76_wcid *wcid, struct ieee80211_sta *sta,
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struct mt76_wcid *wcid, struct ieee80211_sta *sta,
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u32 *tx_info)
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u32 *tx_info)
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{
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{
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struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);
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struct mt76x02_txwi *txwi;
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struct mt76x02_txwi *txwi;
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int err, len = skb->len;
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int err, len = skb->len;
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@ -47,7 +46,7 @@ int mt76x2u_tx_prepare_skb(struct mt76_dev *mdev, void *data,
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mt76x02_insert_hdr_pad(skb);
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mt76x02_insert_hdr_pad(skb);
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txwi = skb_push(skb, sizeof(struct mt76x02_txwi));
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txwi = skb_push(skb, sizeof(struct mt76x02_txwi));
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mt76x2_mac_write_txwi(dev, txwi, skb, wcid, sta, len);
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mt76x02_mac_write_txwi(mdev, txwi, skb, wcid, sta, len);
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return mt76x02u_set_txinfo(skb, wcid, q2ep(q->hw_idx));
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return mt76x02u_set_txinfo(skb, wcid, q2ep(q->hw_idx));
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}
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}
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