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[MIPS] Fix use of ehb instruction for non-R2 configurations.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2006-06-03 22:40:15 +01:00
parent b4ab24e1c8
commit 4277ff5ee5
9 changed files with 27 additions and 26 deletions
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6
arch/mips/kernel/entry.S
View File

@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame
ori v1, v0, TCSTATUS_IXMT
mtc0 v1, CP0_TCSTATUS
andi v0, TCSTATUS_IXMT
ehb
_ehb
mfc0 t0, CP0_TCCONTEXT
DMT 9 # dmt t1
jal mips_ihb
@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame
andi t3, t0, 0xff00
or t2, t2, t3
mtc0 t2, CP0_STATUS
ehb
_ehb
andi t1, t1, VPECONTROL_TE
beqz t1, 1f
EMT
@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame
xori v1, v1, TCSTATUS_IXMT
or v1, v0, v1
mtc0 v1, CP0_TCSTATUS
ehb
_ehb
xor t0, t0, t3
mtc0 t0, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC */

4
arch/mips/kernel/gdb-low.S
View File

@ -291,7 +291,7 @@
ori t1, t2, TCSTATUS_IXMT
mtc0 t1, CP0_TCSTATUS
andi t2, t2, TCSTATUS_IXMT
ehb
_ehb
DMT 9 # dmt t1
jal mips_ihb
nop
@ -310,7 +310,7 @@
xori t1, t1, TCSTATUS_IXMT
or t1, t1, t2
mtc0 t1, CP0_TCSTATUS
ehb
_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_L v0, GDB_FR_STATUS(sp)
LONG_L v1, GDB_FR_EPC(sp)

2
arch/mips/kernel/genex.S
View File

@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp)
mtc0 t0, CP0_TCCONTEXT
xor t1, t1, t0
mtc0 t1, CP0_STATUS
ehb
_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
CLI
move a0, sp

2
arch/mips/kernel/head.S
View File

@ -96,7 +96,7 @@
/* Clear TKSU, leave IXMT */
xori t0, 0x00001800
mtc0 t0, CP0_TCSTATUS
ehb
_ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0 t0, CP0_STATUS
or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr

6
arch/mips/kernel/r4k_switch.S
View File

@ -94,7 +94,7 @@
ori t1, t2, TCSTATUS_IXMT
mtc0 t1, CP0_TCSTATUS
andi t2, t2, TCSTATUS_IXMT
ehb
_ehb
DMT 8 # dmt t0
move t1,ra
jal mips_ihb
@ -109,7 +109,7 @@
or a2, t1
mtc0 a2, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
ehb
_ehb
andi t0, t0, VPECONTROL_TE
beqz t0, 1f
emt
@ -118,7 +118,7 @@
xori t1, t1, TCSTATUS_IXMT
or t1, t1, t2
mtc0 t1, CP0_TCSTATUS
ehb
_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
move v0, a0
jr ra

10
arch/mips/kernel/smtc-asm.S
View File

@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector)
.set noat
/* Disable thread scheduling to make Status update atomic */
DMT 27 # dmt k1
ehb
_ehb
/* Set EXL */
mfc0 k0,CP0_STATUS
ori k0,k0,ST0_EXL
mtc0 k0,CP0_STATUS
ehb
_ehb
/* Thread scheduling now inhibited by EXL. Restore TE state. */
andi k1,k1,VPECONTROL_TE
beqz k1,1f
@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector)
li k1,ST0_CU0
or k1,k1,k0
mtc0 k1,CP0_STATUS
ehb
_ehb
get_saved_sp
/* Interrupting TC will have pre-set values in slots in the new frame */
2: subu k1,k1,PT_SIZE
@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector)
lw k0,PT_TCSTATUS(k1)
/* Write it to TCStatus to restore CU/KSU/IXMT state */
mtc0 k0,$2,1
ehb
_ehb
lw k0,PT_EPC(k1)
mtc0 k0,CP0_EPC
/* Save all will redundantly recompute the SP, but use it for now */
@ -116,7 +116,7 @@ LEAF(self_ipi)
mfc0 t0,CP0_TCSTATUS
ori t1,t0,TCSTATUS_IXMT
mtc0 t1,CP0_TCSTATUS
ehb
_ehb
/* We know we're in kernel mode, so prepare stack frame */
subu t1,sp,PT_SIZE
sw ra,PT_EPC(t1)

4
include/asm-mips/asmmacro.h
View File

@ -26,14 +26,14 @@
ori \reg, \reg, TCSTATUS_IXMT
xori \reg, \reg, TCSTATUS_IXMT
mtc0 \reg, CP0_TCSTATUS
ehb
_ehb
.endm
.macro local_irq_disable reg=t0
mfc0 \reg, CP0_TCSTATUS
ori \reg, \reg, TCSTATUS_IXMT
mtc0 \reg, CP0_TCSTATUS
ehb
_ehb
.endm
#else
.macro local_irq_enable reg=t0

3
include/asm-mips/mipsregs.h
View File

@ -1459,7 +1459,8 @@ static inline void __emt(unsigned int previous)
static inline void __ehb(void)
{
__asm__ __volatile__(
" ehb \n");
" .set mips32r2 \n"
" ehb \n" " .set mips0 \n");
}
/*

16
include/asm-mips/stackframe.h
View File

@ -304,7 +304,7 @@
mfc0 v0, CP0_TCSTATUS
ori v0, TCSTATUS_IXMT
mtc0 v0, CP0_TCSTATUS
ehb
_ehb
DMT 5 # dmt a1
jal mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
@ -325,14 +325,14 @@
* restore TCStatus.IXMT.
*/
LONG_L v1, PT_TCSTATUS(sp)
ehb
_ehb
mfc0 v0, CP0_TCSTATUS
andi v1, TCSTATUS_IXMT
/* We know that TCStatua.IXMT should be set from above */
xori v0, v0, TCSTATUS_IXMT
or v0, v0, v1
mtc0 v0, CP0_TCSTATUS
ehb
_ehb
andi a1, a1, VPECONTROL_TE
beqz a1, 1f
emt
@ -411,7 +411,7 @@
/* Clear TKSU, leave IXMT */
xori t0, 0x00001800
mtc0 t0, CP0_TCSTATUS
ehb
_ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0 t0, CP0_STATUS
ori t0, ST0_EXL | ST0_ERL
@ -438,7 +438,7 @@
* and enable interrupts only for the
* current TC, using the TCStatus register.
*/
ehb
_ehb
mfc0 t0,CP0_TCSTATUS
/* Fortunately CU 0 is in the same place in both registers */
/* Set TCU0, TKSU (for later inversion) and IXMT */
@ -447,7 +447,7 @@
/* Clear TKSU *and* IXMT */
xori t0, 0x00001c00
mtc0 t0, CP0_TCSTATUS
ehb
_ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0 t0, CP0_STATUS
ori t0, ST0_EXL
@ -479,7 +479,7 @@
andi v1, v0, TCSTATUS_IXMT
ori v0, TCSTATUS_IXMT
mtc0 v0, CP0_TCSTATUS
ehb
_ehb
DMT 2 # dmt v0
/*
* We don't know a priori if ra is "live"
@ -495,7 +495,7 @@
xori t0, 0x1e
mtc0 t0, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
ehb
_ehb
andi v0, v0, VPECONTROL_TE
beqz v0, 2f
nop /* delay slot */