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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: dts: imx7d-pico-pi: Separate into cpu and baseboard dts
Separate the old imx7d-pico into cpu (imx7d-pico.dtsi) and baseboard (imx7d-pico-pi.dts) dts so the same cpu dtsi can be used in different baseboards variants. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Vanessa Maegima
Shawn Guo
parent
c5ecd77ec1
commit
41bbeadceb
@ -521,7 +521,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
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imx7d-cl-som-imx7.dtb \
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imx7d-colibri-eval-v3.dtb \
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imx7d-nitrogen7.dtb \
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imx7d-pico.dtb \
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imx7d-pico-pi.dtb \
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imx7d-sbc-imx7.dtb \
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imx7d-sdb.dtb \
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imx7d-sdb-sht11.dtb \
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181
arch/arm/boot/dts/imx7d-pico-pi.dts
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181
arch/arm/boot/dts/imx7d-pico-pi.dts
Normal file
@ -0,0 +1,181 @@
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/*
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* Copyright 2017 NXP
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "imx7d-pico.dtsi"
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/ {
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx7-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,cpu {
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sound-dai = <&sai1>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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status = "okay";
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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codec: sgtl5000@a {
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#sound-dai-cells = <0>;
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reg = <0x0a>;
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compatible = "fsl,sgtl5000";
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_vref_1v8>;
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
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MX7D_PAD_SD2_WP__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
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MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
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MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
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MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
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>;
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};
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pinctrl_usbotg1_pwr: usbotg_pwr {
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fsl,pins = <
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MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
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>;
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};
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};
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@ -100,62 +100,6 @@ reg_vref_1v8: regulator-vref-1v8 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx7-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,cpu {
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sound-dai = <&sai1>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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status = "okay";
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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codec: sgtl5000@a {
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#sound-dai-cells = <0>;
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reg = <0x0a>;
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compatible = "fsl,sgtl5000";
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_vref_1v8>;
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};
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};
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&i2c4 {
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@ -253,35 +197,6 @@ vgen6_reg: vldo4 {
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 { /* Wifi SDIO */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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@ -315,32 +230,6 @@ &wdog1 {
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
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MX7D_PAD_SD2_WP__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
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MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
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@ -354,28 +243,6 @@ MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
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MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
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MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
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>;
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};
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pinctrl_usbotg1_pwr: usbotg_pwr {
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fsl,pins = <
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MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX7D_PAD_SD2_CMD__SD2_CMD 0x59
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